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| author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2020-05-06 18:30:23 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2020-05-06 18:11:34 +0100 |
| commit | 37aa8aa68492deb56f9e4c8b2d00aa5d9dae7da2 (patch) | |
| tree | 954cf651f581a6ef70470192d14e6e8810f175b3 /drivers/spi/spi-dw-mid.c | |
| parent | e7940952644558e680033ae0450978445e53b423 (diff) | |
| download | lwn-37aa8aa68492deb56f9e4c8b2d00aa5d9dae7da2.tar.gz lwn-37aa8aa68492deb56f9e4c8b2d00aa5d9dae7da2.zip | |
spi: dw: Add 'mfld' suffix to Intel Medfield related routines
In order to prepare driver for the extension to support newer hardware,
add 'mfld' suffix to some related functions.
While here, move DMA parameters assignment under existing #ifdef
CONFIG_SPI_DW_MID_DMA.
There is no functional change intended.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20200506153025.21441-6-andriy.shevchenko@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-dw-mid.c')
| -rw-r--r-- | drivers/spi/spi-dw-mid.c | 24 |
1 files changed, 14 insertions, 10 deletions
diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c index 64523e68490d..13b548915c8f 100644 --- a/drivers/spi/spi-dw-mid.c +++ b/drivers/spi/spi-dw-mid.c @@ -34,7 +34,7 @@ static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param) return true; } -static int mid_spi_dma_init(struct dw_spi *dws) +static int mid_spi_dma_init_mfld(struct dw_spi *dws) { struct pci_dev *dma_dev; struct dw_dma_slave *tx = dws->dma_tx; @@ -276,14 +276,23 @@ static void mid_spi_dma_stop(struct dw_spi *dws) } } -static const struct dw_spi_dma_ops mid_dma_ops = { - .dma_init = mid_spi_dma_init, +static const struct dw_spi_dma_ops mfld_dma_ops = { + .dma_init = mid_spi_dma_init_mfld, .dma_exit = mid_spi_dma_exit, .dma_setup = mid_spi_dma_setup, .can_dma = mid_spi_can_dma, .dma_transfer = mid_spi_dma_transfer, .dma_stop = mid_spi_dma_stop, }; + +static void dw_spi_mid_setup_dma_mfld(struct dw_spi *dws) +{ + dws->dma_tx = &mid_dma_tx; + dws->dma_rx = &mid_dma_rx; + dws->dma_ops = &mfld_dma_ops; +} +#else /* CONFIG_SPI_DW_MID_DMA */ +static inline void dw_spi_mid_setup_dma_mfld(struct dw_spi *dws) {} #endif /* Some specific info for SPI0 controller on Intel MID */ @@ -297,7 +306,7 @@ static const struct dw_spi_dma_ops mid_dma_ops = { #define CLK_SPI_CDIV_MASK 0x00000e00 #define CLK_SPI_DISABLE_OFFSET 8 -int dw_spi_mid_init(struct dw_spi *dws) +int dw_spi_mid_init_mfld(struct dw_spi *dws) { void __iomem *clk_reg; u32 clk_cdiv; @@ -314,14 +323,9 @@ int dw_spi_mid_init(struct dw_spi *dws) iounmap(clk_reg); -#ifdef CONFIG_SPI_DW_MID_DMA - dws->dma_tx = &mid_dma_tx; - dws->dma_rx = &mid_dma_rx; - dws->dma_ops = &mid_dma_ops; -#endif - /* Register hook to configure CTRLR0 */ dws->update_cr0 = dw_spi_update_cr0; + dw_spi_mid_setup_dma_mfld(dws); return 0; } |