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| author | peter fuerst <post@pfrst.de> | 2007-02-12 15:20:15 +0100 |
|---|---|---|
| committer | James Bottomley <jejb@mulgrave.il.steeleye.com> | 2007-02-16 09:22:11 -0600 |
| commit | a5d8421b2f03e46f02cc02066b186fdbc0f590a6 (patch) | |
| tree | fe517aae7d78c85af15c3a23810044544a576e52 /drivers/scsi/wd33c93.h | |
| parent | 7de970e11fb832a56c897276967fb0e49f59b313 (diff) | |
| download | lwn-a5d8421b2f03e46f02cc02066b186fdbc0f590a6.tar.gz lwn-a5d8421b2f03e46f02cc02066b186fdbc0f590a6.zip | |
[SCSI] wd33c93: Fast SCSI with WD33C93B
Attached are patches, which help to utilize more of the WD33C93B SCSI
controller's capabilities.
1) Added/changed all the necessary code to enable Burst Mode DMA. Only
Single Byte DMA was used before.
2) Added/changed all the necessary code to enable Fast-10 SCSI transfers.
3) The original driver inadvertently used a transfer period of 1000-800ns
(the lowest possible transfer rate) for asynchronous data transfers,
instead of the (configurable) default period intended for this purpose,
if the target responded to a SDTR not with a Reject-message, but with
a zero-SDTR. This issue was fixed.
Moreover, in case of a Reject the driver used the default-period's
initialization-value instead of its (maybe smaller) current value. The
missing assignment was added.
4) The driver's commandline- and proc-file-interface was augmented to
handle the new options properly.
The WD33C93 manual, found at
http://www.datasheet.in/datasheet-html/W/D/3/WD33C93B_WesternDigital.pdf.html,
was very helpful.
Signed-off-by: peter fuerst <post@pfrst.de>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'drivers/scsi/wd33c93.h')
| -rw-r--r-- | drivers/scsi/wd33c93.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/scsi/wd33c93.h b/drivers/scsi/wd33c93.h index edcb0365cf0c..61ffb860dacc 100644 --- a/drivers/scsi/wd33c93.h +++ b/drivers/scsi/wd33c93.h @@ -155,6 +155,9 @@ #define WD33C93_FS_12_15 OWNID_FS_12 #define WD33C93_FS_16_20 OWNID_FS_16 + /* pass input-clock explicitely. accepted mhz values are 8-10,12-20 */ +#define WD33C93_FS_MHZ(mhz) (mhz) + /* Control register */ #define CTRL_HSP 0x01 #define CTRL_HA 0x02 @@ -253,6 +256,9 @@ struct WD33C93_hostdata { uchar sync_stat[8]; /* status of sync negotiation per target */ uchar no_sync; /* bitmask: don't do sync on these targets */ uchar no_dma; /* set this flag to disable DMA */ + uchar dma_mode; /* DMA Burst Mode or Single Byte DMA */ + uchar fast; /* set this flag to enable Fast SCSI */ + struct sx_period sx_table[9]; /* transfer periods for actual DTC-setting */ #ifdef PROC_INTERFACE uchar proc; /* bitmask: what's in proc output */ #ifdef PROC_STATISTICS |