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author | Philipp Zabel <p.zabel@pengutronix.de> | 2017-08-11 13:03:05 +0200 |
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committer | Philipp Zabel <p.zabel@pengutronix.de> | 2017-10-18 15:51:04 +0200 |
commit | f0e0ada67dfd8342fd411da6e3bff10ff9bcc97b (patch) | |
tree | 00650b981cb356edabe9cfc74c3fc15d591cfb1f /drivers/reset/Kconfig | |
parent | 0af8a137361330af644ae9a3475b328a1dfb7945 (diff) | |
download | lwn-f0e0ada67dfd8342fd411da6e3bff10ff9bcc97b.tar.gz lwn-f0e0ada67dfd8342fd411da6e3bff10ff9bcc97b.zip |
reset: zx2967: use the reset-simple driver
The reset-simple driver can be used without changes.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Diffstat (limited to 'drivers/reset/Kconfig')
-rw-r--r-- | drivers/reset/Kconfig | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 9bdb4fe1b03e..de0090c911cd 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -77,14 +77,14 @@ config RESET_PISTACHIO config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST - default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI + default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX help This enables a simple reset controller driver for reset lines that that can be asserted and deasserted by toggling bits in a contiguous, exclusive register space. Currently this driver supports Altera SoCFPGAs, the RCC reset - controller in STM32 MCUs, and Allwinner SoCs. + controller in STM32 MCUs, Allwinner SoCs, and ZTE's zx2967 family. config RESET_SUNXI bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI @@ -121,12 +121,6 @@ config RESET_UNIPHIER Say Y if you want to control reset signals provided by System Control block, Media I/O block, Peripheral Block. -config RESET_ZX2967 - bool "ZTE ZX2967 Reset Driver" - depends on ARCH_ZX || COMPILE_TEST - help - This enables the reset controller driver for ZTE's zx2967 family. - config RESET_ZYNQ bool "ZYNQ Reset Driver" if COMPILE_TEST default ARCH_ZYNQ |