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authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2024-10-28 15:43:17 +0200
committerMika Westerberg <mika.westerberg@linux.intel.com>2024-11-05 07:48:58 +0200
commitc6235c426d2ac78ab843a55cb1556b0f43175d9e (patch)
tree3299428e8b59784890e7335f9a8a3fc7165b7abf /drivers/pinctrl
parent4cbf2b660f46be45b71d4f67f71495d08bf04371 (diff)
downloadlwn-c6235c426d2ac78ab843a55cb1556b0f43175d9e.tar.gz
lwn-c6235c426d2ac78ab843a55cb1556b0f43175d9e.zip
pinctrl: elkhartlake: Add support for DSW community
Hardware has a DSW (Deep Sleep Well) community that might be exposed by some BIOSes. Add support for it in the driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/intel/pinctrl-elkhartlake.c38
1 files changed, 38 insertions, 0 deletions
diff --git a/drivers/pinctrl/intel/pinctrl-elkhartlake.c b/drivers/pinctrl/intel/pinctrl-elkhartlake.c
index 1678634ebc06..3e45d7fb003a 100644
--- a/drivers/pinctrl/intel/pinctrl-elkhartlake.c
+++ b/drivers/pinctrl/intel/pinctrl-elkhartlake.c
@@ -264,6 +264,43 @@ static const struct intel_pinctrl_soc_data ehl_community1_soc_data = {
.ncommunities = ARRAY_SIZE(ehl_community1),
};
+static const struct pinctrl_pin_desc ehl_community2_pins[] = {
+ /* DSW */
+ PINCTRL_PIN(0, "BATLOWB"),
+ PINCTRL_PIN(1, "ACPRESENT"),
+ PINCTRL_PIN(2, "LAN_WAKEB"),
+ PINCTRL_PIN(3, "PWRBTNB"),
+ PINCTRL_PIN(4, "SLP_S3B"),
+ PINCTRL_PIN(5, "SLP_S4B"),
+ PINCTRL_PIN(6, "SLP_AB"),
+ PINCTRL_PIN(7, "GPD_7"),
+ PINCTRL_PIN(8, "SUSCLK"),
+ PINCTRL_PIN(9, "SLP_WLANB"),
+ PINCTRL_PIN(10, "SLP_S5B"),
+ PINCTRL_PIN(11, "LANPHYPC"),
+ PINCTRL_PIN(12, "INPUT3VSEL"),
+ PINCTRL_PIN(13, "SLP_LANB"),
+ PINCTRL_PIN(14, "SLP_SUSB"),
+ PINCTRL_PIN(15, "WAKEB"),
+ PINCTRL_PIN(16, "DRAM_RESETB"),
+};
+
+static const struct intel_padgroup ehl_community2_gpps[] = {
+ EHL_GPP(0, 0, 16), /* DSW */
+};
+
+static const struct intel_community ehl_community2[] = {
+ EHL_COMMUNITY(0, 0, 16, ehl_community2_gpps),
+};
+
+static const struct intel_pinctrl_soc_data ehl_community2_soc_data = {
+ .uid = "2",
+ .pins = ehl_community2_pins,
+ .npins = ARRAY_SIZE(ehl_community2_pins),
+ .communities = ehl_community2,
+ .ncommunities = ARRAY_SIZE(ehl_community2),
+};
+
static const struct pinctrl_pin_desc ehl_community3_pins[] = {
/* CPU */
PINCTRL_PIN(0, "HDACPU_SDI"),
@@ -474,6 +511,7 @@ static const struct intel_pinctrl_soc_data ehl_community5_soc_data = {
static const struct intel_pinctrl_soc_data *ehl_soc_data_array[] = {
&ehl_community0_soc_data,
&ehl_community1_soc_data,
+ &ehl_community2_soc_data,
&ehl_community3_soc_data,
&ehl_community4_soc_data,
&ehl_community5_soc_data,