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author | Linus Torvalds <torvalds@linux-foundation.org> | 2020-04-02 15:47:18 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2020-04-02 15:47:18 -0700 |
commit | bc3b3f4bfbded031a11c4284106adddbfacd05bb (patch) | |
tree | ce31309cc4c4dc85f89ee136154dd8ee38eef925 /drivers/pinctrl/tegra/pinctrl-tegra.c | |
parent | 11786191e2d946410cf5fde482b10cdd5356e76c (diff) | |
parent | c42f69b4207e104229242c3d9da43b55d4b95d6d (diff) | |
download | lwn-bc3b3f4bfbded031a11c4284106adddbfacd05bb.tar.gz lwn-bc3b3f4bfbded031a11c4284106adddbfacd05bb.zip |
Merge tag 'pinctrl-v5.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v5.7 kernel cycle.
There are no core changes this time, only driver developments:
- New driver for the Dialog Semiconductor DA9062 Power Management
Integrated Circuit (PMIC).
- Renesas SH-PFC has improved consistency, with group and register
checks in the configuration checker.
- New subdriver for the Qualcomm IPQ6018.
- Add the RGMII pin control functionality to Qualcomm IPQ8064.
- Performance and code quality cleanups in the Mediatek driver.
- Improve the Broadcom BCM2835 support to cover all the GPIOs that
exist in it.
- The Allwinner/Sunxi driver properly masks non-wakeup IRQs on
suspend.
- Add some missing groups and functions to the Ingenic driver.
- Convert some of the Freescale device tree bindings to use the new
and all improved JSON YAML markup.
- Refactorings and support for the SFIO/GPIO in the Tegra194 SoC
driver.
- Support high impedance mode in the Spreadtrum/Unisoc driver"
* tag 'pinctrl-v5.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (64 commits)
pinctrl: qcom: fix compilation error
pinctrl: qcom: use scm_call to route GPIO irq to Apps
pinctrl: sprd: Add pin high impedance mode support
pinctrl: sprd: Use the correct pin output configuration
pinctrl: tegra: Add SFIO/GPIO programming on Tegra194
pinctrl: tegra: Renumber the GG.0 and GG.1 pins
pinctrl: tegra: Do not add default pin range on Tegra194
pinctrl: tegra: Pass struct tegra_pmx for pin range check
pinctrl: tegra: Fix "Scmitt" -> "Schmitt" typo
pinctrl: tegra: Fix whitespace issues for improved readability
pinctrl: mediatek: Use scnprintf() for avoiding potential buffer overflow
pinctrl: freescale: drop the dependency on ARM64 for i.MX8M
Revert "pinctrl: mvebu: armada-37xx: use use platform api"
dt-bindings: pinctrl: at91: Fix a typo ("descibe")
pinctrl: meson: add tsin pinctrl for meson gxbb/gxl/gxm
pinctrl: sprd: Fix the kconfig warning
pinctrl: ingenic: add hdmi-ddc pin control group
pinctrl: sirf/atlas7: Replace zero-length array with flexible-array member
pinctrl: sprd: Allow the SPRD pinctrl driver building into a module
pinctrl: Export some needed symbols at module load time
...
Diffstat (limited to 'drivers/pinctrl/tegra/pinctrl-tegra.c')
-rw-r--r-- | drivers/pinctrl/tegra/pinctrl-tegra.c | 52 |
1 files changed, 49 insertions, 3 deletions
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index cefbbb8d1a68..21661f6490d6 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -275,11 +275,57 @@ static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev, return 0; } +static int tegra_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + const struct tegra_pingroup *group; + u32 value; + + if (!pmx->soc->sfsel_in_mux) + return 0; + + group = &pmx->soc->groups[offset]; + + if (group->mux_reg < 0 || group->sfsel_bit < 0) + return -EINVAL; + + value = pmx_readl(pmx, group->mux_bank, group->mux_reg); + value &= ~BIT(group->sfsel_bit); + pmx_writel(pmx, value, group->mux_bank, group->mux_reg); + + return 0; +} + +static void tegra_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + const struct tegra_pingroup *group; + u32 value; + + if (!pmx->soc->sfsel_in_mux) + return; + + group = &pmx->soc->groups[offset]; + + if (group->mux_reg < 0 || group->sfsel_bit < 0) + return; + + value = pmx_readl(pmx, group->mux_bank, group->mux_reg); + value |= BIT(group->sfsel_bit); + pmx_writel(pmx, value, group->mux_bank, group->mux_reg); +} + static const struct pinmux_ops tegra_pinmux_ops = { .get_functions_count = tegra_pinctrl_get_funcs_count, .get_function_name = tegra_pinctrl_get_func_name, .get_function_groups = tegra_pinctrl_get_func_groups, .set_mux = tegra_pinctrl_set_mux, + .gpio_request_enable = tegra_pinctrl_gpio_request_enable, + .gpio_disable_free = tegra_pinctrl_gpio_disable_free, }; static int tegra_pinconf_reg(struct tegra_pmx *pmx, @@ -689,12 +735,12 @@ const struct dev_pm_ops tegra_pinctrl_pm = { .resume = &tegra_pinctrl_resume }; -static bool gpio_node_has_range(const char *compatible) +static bool tegra_pinctrl_gpio_node_has_range(struct tegra_pmx *pmx) { struct device_node *np; bool has_prop = false; - np = of_find_compatible_node(NULL, NULL, compatible); + np = of_find_compatible_node(NULL, NULL, pmx->soc->gpio_compatible); if (!np) return has_prop; @@ -794,7 +840,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev, tegra_pinctrl_clear_parked_bits(pmx); - if (!gpio_node_has_range(pmx->soc->gpio_compatible)) + if (pmx->soc->ngpios > 0 && !tegra_pinctrl_gpio_node_has_range(pmx)) pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range); platform_set_drvdata(pdev, pmx); |