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| author | Siddharth Vadapalli <s-vadapalli@ti.com> | 2024-10-10 20:18:45 +0530 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2024-10-11 13:59:44 +0530 |
| commit | 9e544d46a2d11a0cb8b30d8ad4409c59bc168ce2 (patch) | |
| tree | b0bc84132469cb02e3b0d12d24dff6b77c7a0e39 /drivers/phy | |
| parent | bbcc9e2bde693ec3fc6aab650abaf748eb9f38f9 (diff) | |
| download | lwn-9e544d46a2d11a0cb8b30d8ad4409c59bc168ce2.tar.gz lwn-9e544d46a2d11a0cb8b30d8ad4409c59bc168ce2.zip | |
phy: ti: gmii-sel: Enable USXGMII mode for J7200
TI's J7200 SoC supports USXGMII mode with the CPSW5G instance's MAC Port1.
Add USXGMII mode to the extra_modes member of J7200's SoC data.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20241010144845.2555983-1-s-vadapalli@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy')
| -rw-r--r-- | drivers/phy/ti/phy-gmii-sel.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c index 103b266fec77..e0ca59ae3153 100644 --- a/drivers/phy/ti/phy-gmii-sel.c +++ b/drivers/phy/ti/phy-gmii-sel.c @@ -230,7 +230,8 @@ static const struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = { .use_of_data = true, .regfields = phy_gmii_sel_fields_am654, - .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII), + .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) | + BIT(PHY_INTERFACE_MODE_USXGMII), .num_ports = 4, .num_qsgmii_main_ports = 1, }; |