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| author | Sam Protsenko <semen.protsenko@linaro.org> | 2023-08-18 22:17:28 -0500 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2023-08-22 19:41:15 +0530 |
| commit | 255ec3879dd4d585799fd8d8a94a335eaf84d2ec (patch) | |
| tree | 1d12c69f9b40aa91090976239a0b7908ad467177 /drivers/phy/samsung | |
| parent | 6b34ec66e7e7351b9a0a1eba8f57eb46ddeabf1e (diff) | |
| download | lwn-255ec3879dd4d585799fd8d8a94a335eaf84d2ec.tar.gz lwn-255ec3879dd4d585799fd8d8a94a335eaf84d2ec.zip | |
phy: exynos5-usbdrd: Add 26MHz ref clk support
Modern Exynos chips (like Exynos850) might have 26 MHz OSCCLK external
clock, which is also used as a PHY reference clock. For some USB PHY
controllers (e.g USB DRD PHY block on Exynos850) there is no need to set
the refclk frequency at all (and corresponding bits in CLKRSTCTRL[7:5]
are marked RESERVED), so that value won't be set in the driver. But
even in that case, 26 MHz support still has to be added, otherwise
exynos5_rate_to_clk() fails, which leads in turn to probe error.
Add the correct value for 26MHz refclk to make it possible to add
support for new Exynos USB DRD PHY controllers.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230819031731.22618-6-semen.protsenko@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy/samsung')
| -rw-r--r-- | drivers/phy/samsung/phy-exynos5-usbdrd.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index 1ece4a1a1a6e..41508db87b9b 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -30,6 +30,7 @@ #define EXYNOS5_FSEL_19MHZ2 0x3 #define EXYNOS5_FSEL_20MHZ 0x4 #define EXYNOS5_FSEL_24MHZ 0x5 +#define EXYNOS5_FSEL_26MHZ 0x82 #define EXYNOS5_FSEL_50MHZ 0x7 /* Exynos5: USB 3.0 DRD PHY registers */ @@ -244,6 +245,9 @@ static unsigned int exynos5_rate_to_clk(unsigned long rate, u32 *reg) case 24 * MHZ: *reg = EXYNOS5_FSEL_24MHZ; break; + case 26 * MHZ: + *reg = EXYNOS5_FSEL_26MHZ; + break; case 50 * MHZ: *reg = EXYNOS5_FSEL_50MHZ; break; |