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| author | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2023-01-14 12:40:05 +0530 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2023-01-17 11:54:57 +0530 |
| commit | 692b65516080302c2782bb7bae12e086f137313d (patch) | |
| tree | d5e4d993833ef6feea0d0a972193a2a9c04c66f8 /drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h | |
| parent | f89dcb24e2ec7edc80f2f56dfa8b3fd22f311561 (diff) | |
| download | lwn-692b65516080302c2782bb7bae12e086f137313d.tar.gz lwn-692b65516080302c2782bb7bae12e086f137313d.zip | |
phy: qcom-qmp-ufs: Add HS G4 mode support to SM8250 SoC
UFS PHY in SM8250 SoC is capable of operating at HS G4 mode. Hence, add the
required register settings using the tables_hs_g4 struct instance. This
also requires a separate qmp_phy_cfg for SM8250 instead of reusing SM8150.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230114071009.88102-9-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h')
| -rw-r--r-- | drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h index 43255e8bf038..07959964fcf6 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h @@ -16,6 +16,7 @@ #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 +#define QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 |