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| author | Mrinmay Sarkar <quic_msarkar@quicinc.com> | 2023-07-14 10:38:36 +0530 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2023-07-18 11:37:10 +0530 |
| commit | a05b6d5135ec3e65520ae0eaa1b24d4c6549424e (patch) | |
| tree | e41b6083aec214f10bd3c1ec97c2a68a644f0eff /drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h | |
| parent | fd2d4e4c19864fdd400d961de899163323ab7fa9 (diff) | |
| download | lwn-a05b6d5135ec3e65520ae0eaa1b24d4c6549424e.tar.gz lwn-a05b6d5135ec3e65520ae0eaa1b24d4c6549424e.zip | |
phy: qcom-qmp-pcie: add support for sa8775p
Add support for dual and four lane PHY found on sa8755p platform.
Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
Link: https://lore.kernel.org/r/1689311319-22054-5-git-send-email-quic_msarkar@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h')
| -rw-r--r-- | drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h index a3a056741fc7..cdf8c04ea078 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h @@ -7,6 +7,7 @@ #define QCOM_PHY_QMP_PCS_PCIE_V5_20_H_ /* Only for QMP V5_20 PHY - PCIe PCS registers */ +#define QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2 0x00c #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084 #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 |