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| author | Rohit Agarwal <quic_rohiagar@quicinc.com> | 2023-03-17 12:08:34 +0530 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2023-03-31 19:24:24 +0530 |
| commit | 92bd868f529a7771f15a141e8db6b6b62b32310a (patch) | |
| tree | 950f93ed4adf4539fbc135b39705b0645feb146b /drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h | |
| parent | 0d678713118352614b14aba0c1fb066b1ba39f53 (diff) | |
| download | lwn-92bd868f529a7771f15a141e8db6b6b62b32310a.tar.gz lwn-92bd868f529a7771f15a141e8db6b6b62b32310a.zip | |
phy: qcom-qmp: Add support for SDX65 QMP PCIe PHY
The PCIe PHY version used in SDX65 is v5.20 which has different register
offsets compared to the v5.0x and v4.0x PHYs. So separate register defines are
used for init sequence and PHY status.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Link: https://lore.kernel.org/r/1679035114-19879-3-git-send-email-quic_rohiagar@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h')
| -rw-r--r-- | drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h index 3d9713d348fe..a3a056741fc7 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h @@ -12,8 +12,11 @@ #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0 #define QPHY_V5_20_PCS_PCIE_PRESET_P10_POST 0x0e0 +#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184 +#define QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2 0xa24 +#define QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2 0xa28 #endif |