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authorChunfeng Yun <chunfeng.yun@mediatek.com>2022-09-20 17:00:36 +0800
committerVinod Koul <vkoul@kernel.org>2022-09-24 11:57:51 +0530
commitd36d69a5517bb4e90a6ba07b043806bffffe19fb (patch)
tree3c2862daf5a2e2ce3be177e59c33ba15e09a7310 /drivers/phy/mediatek
parentbd4ba730ff28985c0ecb49da1c6f18488666aa4f (diff)
downloadlwn-d36d69a5517bb4e90a6ba07b043806bffffe19fb.tar.gz
lwn-d36d69a5517bb4e90a6ba07b043806bffffe19fb.zip
phy: mediatek: mipi: mt8183: use GENMASK to generate bits mask
Use GENMASK() macro to generate bits mask Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220920090038.15133-17-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy/mediatek')
-rw-r--r--drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
index 99108426d57c..1ec71ba2407e 100644
--- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
+++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
@@ -18,7 +18,7 @@
#define RG_DSI_PAD_TIEL_SEL BIT(8)
#define MIPITX_VOLTAGE_SEL 0x0010
-#define RG_DSI_HSTX_LDO_REF_SEL (0xf << 6)
+#define RG_DSI_HSTX_LDO_REF_SEL GENMASK(9, 6)
#define MIPITX_PLL_PWR 0x0028
#define MIPITX_PLL_CON0 0x002c
@@ -26,7 +26,7 @@
#define MIPITX_PLL_CON2 0x0034
#define MIPITX_PLL_CON3 0x0038
#define MIPITX_PLL_CON4 0x003c
-#define RG_DSI_PLL_IBIAS (3 << 10)
+#define RG_DSI_PLL_IBIAS GENMASK(11, 10)
#define MIPITX_D2P_RTCODE 0x0100
#define MIPITX_D2_SW_CTL_EN 0x0144
@@ -41,7 +41,7 @@
#define AD_DSI_PLL_SDM_ISO_EN BIT(1)
#define RG_DSI_PLL_EN BIT(4)
-#define RG_DSI_PLL_POSDIV (0x7 << 8)
+#define RG_DSI_PLL_POSDIV GENMASK(10, 8)
static int mtk_mipi_tx_pll_enable(struct clk_hw *hw)
{