diff options
| author | Pali Rohár <pali@kernel.org> | 2021-08-27 11:27:52 +0200 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2021-08-27 12:20:33 +0100 |
| commit | b756bbec9cdd83c4702552d30c9fb11d07487000 (patch) | |
| tree | 6686e95db762154b1762e5a582173aed33c6c6e3 /drivers/phy/marvell/phy-mvebu-a3700-comphy.c | |
| parent | 3f141ad617458a1dcbd8a473acb7d05fb35ac545 (diff) | |
| download | lwn-b756bbec9cdd83c4702552d30c9fb11d07487000.tar.gz lwn-b756bbec9cdd83c4702552d30c9fb11d07487000.zip | |
phy: marvell: phy-mvebu-a3700-comphy: Rename HS-SGMMI to 2500Base-X
Comphy phy mode 0x3 is incorrectly named. It is not SGMII but rather
2500Base-X mode which runs at 3.125 Gbps speed.
Rename macro names and comments to 2500Base-X.
Signed-off-by: Pali Rohár <pali@kernel.org>
Fixes: 9695375a3f4a ("phy: add A3700 COMPHY support")
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/phy/marvell/phy-mvebu-a3700-comphy.c')
| -rw-r--r-- | drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c index 810f25a47632..cc534a5c4b3b 100644 --- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c +++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c @@ -29,7 +29,7 @@ #define COMPHY_FW_MODE_SATA 0x1 #define COMPHY_FW_MODE_SGMII 0x2 -#define COMPHY_FW_MODE_HS_SGMII 0x3 +#define COMPHY_FW_MODE_2500BASEX 0x3 #define COMPHY_FW_MODE_USB3H 0x4 #define COMPHY_FW_MODE_USB3D 0x5 #define COMPHY_FW_MODE_PCIE 0x6 @@ -40,7 +40,7 @@ #define COMPHY_FW_SPEED_1_25G 0 /* SGMII 1G */ #define COMPHY_FW_SPEED_2_5G 1 -#define COMPHY_FW_SPEED_3_125G 2 /* SGMII 2.5G */ +#define COMPHY_FW_SPEED_3_125G 2 /* 2500BASE-X */ #define COMPHY_FW_SPEED_5G 3 #define COMPHY_FW_SPEED_5_15625G 4 /* XFI 5G */ #define COMPHY_FW_SPEED_6G 5 @@ -84,14 +84,14 @@ static const struct mvebu_a3700_comphy_conf mvebu_a3700_comphy_modes[] = { MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII, 1, COMPHY_FW_MODE_SGMII), MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX, 1, - COMPHY_FW_MODE_HS_SGMII), + COMPHY_FW_MODE_2500BASEX), /* lane 1 */ MVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE, 0, COMPHY_FW_MODE_PCIE), MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII, 0, COMPHY_FW_MODE_SGMII), MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX, 0, - COMPHY_FW_MODE_HS_SGMII), + COMPHY_FW_MODE_2500BASEX), /* lane 2 */ MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA, 0, COMPHY_FW_MODE_SATA), @@ -205,7 +205,7 @@ static int mvebu_a3700_comphy_power_on(struct phy *phy) COMPHY_FW_SPEED_1_25G); break; case PHY_INTERFACE_MODE_2500BASEX: - dev_dbg(lane->dev, "set lane %d to HS SGMII mode\n", + dev_dbg(lane->dev, "set lane %d to 2500BASEX mode\n", lane->id); fw_param = COMPHY_FW_NET(fw_mode, lane->port, COMPHY_FW_SPEED_3_125G); |