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| author | Marek Vasut <marex@denx.de> | 2022-04-13 16:07:10 +0200 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2022-04-20 14:45:55 +0530 |
| commit | f7f9abc5eab9d10561d74b20b3e284649e07d82f (patch) | |
| tree | eca2af94d44afb4b7be947fe9c2adafa115793dd /drivers/phy/freescale | |
| parent | 1599069a62c6179fdde9f6e5b54d44531064a79c (diff) | |
| download | lwn-f7f9abc5eab9d10561d74b20b3e284649e07d82f.tar.gz lwn-f7f9abc5eab9d10561d74b20b3e284649e07d82f.zip | |
phy: freescale: imx8m-pcie: Handle IMX8_PCIE_REFCLK_PAD_UNUSED
The 'fsl,refclk-pad-mode' DT property used to select clock source for
PCIe PHY can have either of three values, IMX8_PCIE_REFCLK_PAD_INPUT,
IMX8_PCIE_REFCLK_PAD_OUTPUT, IMX8_PCIE_REFCLK_PAD_UNUSED. The first
two options are handled correctly by the driver, the last one is not,
this patch implements support for the last option.
The IMX8_PCIE_REFCLK_PAD_INPUT means PCIE_RESREF is PHY clock input,
the IMX8_PCIE_REFCLK_PAD_OUTPUT means PHY clock are sourced from SoC
internal PLL and output to PCIE_RESREF external IO pin. The last
IMX8_PCIE_REFCLK_PAD_UNUSED is a combination of previous two, PHY
clock are sourced from SoC internal PLL and not output anywhere.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
To: linux-phy@lists.infradead.org
Link: https://lore.kernel.org/r/20220413140710.10074-1-marex@denx.de
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy/freescale')
| -rw-r--r-- | drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c index f1eb03ba25d6..ad7d2edfc414 100644 --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c @@ -94,15 +94,21 @@ static int imx8_pcie_phy_init(struct phy *phy) IMX8MM_GPR_PCIE_CMN_RST); usleep_range(200, 500); - if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT) { + if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT || + pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) { /* Configure the pad as input */ val = readl(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061); writel(val & ~ANA_PLL_CLK_OUT_TO_EXT_IO_EN, imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061); - } else if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT) { + } else { /* Configure the PHY to output the refclock via pad */ writel(ANA_PLL_CLK_OUT_TO_EXT_IO_EN, imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061); + } + + if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT || + pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) { + /* Source clock from SoC internal PLL */ writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL, imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062); writel(AUX_PLL_REFCLK_SEL_SYS_PLL, |