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| author | Jeongtae Park <jtp.park@samsung.com> | 2023-09-05 21:33:09 +0900 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2023-09-05 15:51:18 +0100 |
| commit | 7625df9f4b255eb9d56885e25c564d7e794c6da1 (patch) | |
| tree | 5f794f0b6732a78ea064fd70972a64e0e123c57f /drivers/perf/cxl_pmu.c | |
| parent | e1df27213941725962f68c64349bbcc60ece0314 (diff) | |
| download | lwn-7625df9f4b255eb9d56885e25c564d7e794c6da1.tar.gz lwn-7625df9f4b255eb9d56885e25c564d7e794c6da1.zip | |
perf: CXL: fix mismatched number of counters mask
The number of Count Units field is described as 6 bits long
in the CXL 3.0 specification. However, its mask value was
only declared as 5 bits long.
Signed-off-by: Jeongtae Park <jtp.park@samsung.com>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20230905123309.775854-1-jtp.park@samsung.com
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'drivers/perf/cxl_pmu.c')
| -rw-r--r-- | drivers/perf/cxl_pmu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/perf/cxl_pmu.c b/drivers/perf/cxl_pmu.c index 0a8f597e695b..365d964b0f6a 100644 --- a/drivers/perf/cxl_pmu.c +++ b/drivers/perf/cxl_pmu.c @@ -25,7 +25,7 @@ #include "../cxl/pmu.h" #define CXL_PMU_CAP_REG 0x0 -#define CXL_PMU_CAP_NUM_COUNTERS_MSK GENMASK_ULL(4, 0) +#define CXL_PMU_CAP_NUM_COUNTERS_MSK GENMASK_ULL(5, 0) #define CXL_PMU_CAP_COUNTER_WIDTH_MSK GENMASK_ULL(15, 8) #define CXL_PMU_CAP_NUM_EVN_CAP_REG_SUP_MSK GENMASK_ULL(24, 20) #define CXL_PMU_CAP_FILTERS_SUP_MSK GENMASK_ULL(39, 32) |