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| author | Thierry Reding <treding@nvidia.com> | 2016-02-09 15:52:33 +0100 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2016-03-08 15:42:56 -0600 |
| commit | e32faa303f7f63bad8f9f04267878d61e0f7e0b5 (patch) | |
| tree | 61ca8fb5c0001b9d624b71c9271932a3bf656355 /drivers/pci | |
| parent | 56e75e2a15d0b28261503d415eb56bb4c2b92be5 (diff) | |
| download | lwn-e32faa303f7f63bad8f9f04267878d61e0f7e0b5.tar.gz lwn-e32faa303f7f63bad8f9f04267878d61e0f7e0b5.zip | |
PCI: tegra: Remove misleading PHYS_OFFSET
BARs are disabled when the size register is 0, so it's misleading to write
a base address into the start register.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/host/pci-tegra.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 7bda73bf7c5e..68d1f41b3cbf 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -771,7 +771,7 @@ static void tegra_pcie_setup_translations(struct tegra_pcie *pcie) afi_writel(pcie, 0, AFI_FPCI_BAR5); /* map all upstream transactions as uncached */ - afi_writel(pcie, PHYS_OFFSET, AFI_CACHE_BAR0_ST); + afi_writel(pcie, 0, AFI_CACHE_BAR0_ST); afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ); afi_writel(pcie, 0, AFI_CACHE_BAR1_ST); afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ); |