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| author | Jay Fang <f.fangjian@huawei.com> | 2018-03-12 17:13:32 +0800 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2018-03-21 16:23:55 -0500 |
| commit | 1acfb9b7ee0b1881bb8e875b6757976e48293ec4 (patch) | |
| tree | d23a90908da7413d67775edb40d452c7e2913007 /drivers/pci/slot.c | |
| parent | 7928b2cbe55b2a410a0f5c1f154610059c57b1b2 (diff) | |
| download | lwn-1acfb9b7ee0b1881bb8e875b6757976e48293ec4.tar.gz lwn-1acfb9b7ee0b1881bb8e875b6757976e48293ec4.zip | |
PCI: Add decoding for 16 GT/s link speed
PCIe 4.0 defines the 16.0 GT/s link speed. Links can run at that speed
without any Linux changes, but previously their sysfs "max_link_speed" and
"current_link_speed" files contained "Unknown speed", not the expected
"16.0 GT/s".
Add decoding for the new 16 GT/s link speed.
Signed-off-by: Jay Fang <f.fangjian@huawei.com>
[bhelgaas: add PCI_EXP_LNKCAP2_SLS_16_0GB]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Dongdong Liu <liudongdong3@huawei.com>
Diffstat (limited to 'drivers/pci/slot.c')
| -rw-r--r-- | drivers/pci/slot.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/pci/slot.c b/drivers/pci/slot.c index d10f556dc03e..191893e19d5c 100644 --- a/drivers/pci/slot.c +++ b/drivers/pci/slot.c @@ -76,6 +76,7 @@ static const char *pci_bus_speed_strings[] = { "2.5 GT/s PCIe", /* 0x14 */ "5.0 GT/s PCIe", /* 0x15 */ "8.0 GT/s PCIe", /* 0x16 */ + "16.0 GT/s PCIe", /* 0x17 */ }; static ssize_t bus_speed_read(enum pci_bus_speed speed, char *buf) |