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| author | Bjorn Helgaas <bhelgaas@google.com> | 2023-10-28 13:31:05 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2023-10-28 13:31:05 -0500 |
| commit | 5897c174028a6a05169b6ecdbcd20fe4d1a8bcda (patch) | |
| tree | 184ebbe7e6fff66e04d53bbc416ecde1f538612f /drivers/pci/pcie/ptm.c | |
| parent | 65de3fd8f5c8a910e5bebc0607f8790158ad673a (diff) | |
| parent | 8a0395578a9bb8937d1cc88c3f2e17e437467c2d (diff) | |
| download | lwn-5897c174028a6a05169b6ecdbcd20fe4d1a8bcda.tar.gz lwn-5897c174028a6a05169b6ecdbcd20fe4d1a8bcda.zip | |
Merge branch 'pci/field-get'
- Use FIELD_GET()/FIELD_PREP() when possible throughout drivers/pci/ (Ilpo
Järvinen, Bjorn Helgaas)
- Rework DPC control programming for clarity (Ilpo Järvinen)
* pci/field-get:
PCI/portdrv: Use FIELD_GET()
PCI/VC: Use FIELD_GET()
PCI/PTM: Use FIELD_GET()
PCI/PME: Use FIELD_GET()
PCI/ATS: Use FIELD_GET()
PCI/ATS: Show PASID Capability register width in bitmasks
PCI: Use FIELD_GET() in Sapphire RX 5600 XT Pulse quirk
PCI: Use FIELD_GET()
PCI/MSI: Use FIELD_GET/PREP()
PCI/DPC: Use defines with DPC reason fields
PCI/DPC: Use defined fields with DPC_CTL register
PCI/DPC: Use FIELD_GET()
PCI: hotplug: Use FIELD_GET/PREP()
PCI: dwc: Use FIELD_GET/PREP()
PCI: cadence: Use FIELD_GET()
PCI: Use FIELD_GET() to extract Link Width
PCI: mvebu: Use FIELD_PREP() with Link Width
PCI: tegra194: Use FIELD_GET()/FIELD_PREP() with Link Width fields
# Conflicts:
# drivers/pci/controller/dwc/pcie-tegra194.c
Diffstat (limited to 'drivers/pci/pcie/ptm.c')
| -rw-r--r-- | drivers/pci/pcie/ptm.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/pci/pcie/ptm.c b/drivers/pci/pcie/ptm.c index b4e5f553467c..7cfb6c0d5dcb 100644 --- a/drivers/pci/pcie/ptm.c +++ b/drivers/pci/pcie/ptm.c @@ -4,6 +4,7 @@ * Copyright (c) 2016, Intel Corporation. */ +#include <linux/bitfield.h> #include <linux/module.h> #include <linux/init.h> #include <linux/pci.h> @@ -53,7 +54,7 @@ void pci_ptm_init(struct pci_dev *dev) pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_PTM, sizeof(u32)); pci_read_config_dword(dev, ptm + PCI_PTM_CAP, &cap); - dev->ptm_granularity = (cap & PCI_PTM_GRANULARITY_MASK) >> 8; + dev->ptm_granularity = FIELD_GET(PCI_PTM_GRANULARITY_MASK, cap); /* * Per the spec recommendation (PCIe r6.0, sec 7.9.15.3), select the @@ -146,7 +147,7 @@ static int __pci_enable_ptm(struct pci_dev *dev) ctrl |= PCI_PTM_CTRL_ENABLE; ctrl &= ~PCI_PTM_GRANULARITY_MASK; - ctrl |= dev->ptm_granularity << 8; + ctrl |= FIELD_PREP(PCI_PTM_GRANULARITY_MASK, dev->ptm_granularity); if (dev->ptm_root) ctrl |= PCI_PTM_CTRL_ROOT; |