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| author | Shaohua Li <shaohua.li@intel.com> | 2006-05-26 10:58:27 +0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2006-06-21 12:00:00 -0700 |
| commit | 99dc804d9bcc2c53f4c20c291bf4e185312a1a0c (patch) | |
| tree | 4798f39176d0f8fe06de446d74cf94ba48423aa9 /drivers/pci/msi.c | |
| parent | 020d502488bebdbc1b2c2828d996f04e563f082a (diff) | |
| download | lwn-99dc804d9bcc2c53f4c20c291bf4e185312a1a0c.tar.gz lwn-99dc804d9bcc2c53f4c20c291bf4e185312a1a0c.zip | |
[PATCH] PCI: disable msi mode in pci_disable_device
Brice said the pci_save_msi_state breaks his driver in his special usage
(not in suspend/resume), as pci_save_msi_state will disable msi mode. In
his usage, pci_save_state will be called at runtime, and later (after
the device operates for some time and has an error) pci_restore_state
will be called.
In another hand, suspend/resume needs disable msi mode, as device should
stop working completely. This patch try to workaround this issue.
Drivers are expected call pci_disable_device in suspend time after
pci_save_state.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/pci/msi.c')
| -rw-r--r-- | drivers/pci/msi.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c index 9c69b6966e79..3ec558dc6523 100644 --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -453,9 +453,11 @@ static void enable_msi_mode(struct pci_dev *dev, int pos, int type) /* Set enabled bits to single MSI & enable MSI_enable bit */ msi_enable(control, 1); pci_write_config_word(dev, msi_control_reg(pos), control); + dev->msi_enabled = 1; } else { msix_enable(control); pci_write_config_word(dev, msi_control_reg(pos), control); + dev->msix_enabled = 1; } if (pci_find_capability(dev, PCI_CAP_ID_EXP)) { /* PCI Express Endpoint device detected */ @@ -472,9 +474,11 @@ void disable_msi_mode(struct pci_dev *dev, int pos, int type) /* Set enabled bits to single MSI & enable MSI_enable bit */ msi_disable(control); pci_write_config_word(dev, msi_control_reg(pos), control); + dev->msi_enabled = 0; } else { msix_disable(control); pci_write_config_word(dev, msi_control_reg(pos), control); + dev->msix_enabled = 0; } if (pci_find_capability(dev, PCI_CAP_ID_EXP)) { /* PCI Express Endpoint device detected */ @@ -549,7 +553,6 @@ int pci_save_msi_state(struct pci_dev *dev) pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]); if (control & PCI_MSI_FLAGS_MASKBIT) pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]); - disable_msi_mode(dev, pos, PCI_CAP_ID_MSI); save_state->cap_nr = PCI_CAP_ID_MSI; pci_add_saved_cap(dev, save_state); return 0; @@ -639,7 +642,6 @@ int pci_save_msix_state(struct pci_dev *dev) } dev->irq = temp; - disable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); save_state->cap_nr = PCI_CAP_ID_MSIX; pci_add_saved_cap(dev, save_state); return 0; |