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authorLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2017-06-28 15:13:56 -0500
committerBjorn Helgaas <bhelgaas@google.com>2017-07-02 16:14:23 -0500
commit295aeb98a3220fe09c81fd4c8ad6e7884e05193d (patch)
tree388c89811f8eaae9c2d91fdb6458666bff436caf /drivers/pci/dwc
parent97ad2bdcbe8598a69ee1f372ed6c0fbdb2869218 (diff)
downloadlwn-295aeb98a3220fe09c81fd4c8ad6e7884e05193d.tar.gz
lwn-295aeb98a3220fe09c81fd4c8ad6e7884e05193d.zip
PCI: designware: Convert PCI scan API to pci_scan_root_bus_bridge()
The introduction of pci_scan_root_bus_bridge() provides a PCI core API to scan a PCI root bus backed by an already initialized struct pci_host_bridge object, which simplifies the bus scan interface and makes the PCI scan root bus interface easier to generalize as members are added to the struct pci_host_bridge. Convert PCI designware host code to pci_scan_root_bus_bridge() to improve the PCI root bus scanning interface. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Joao Pinto <Joao.Pinto@synopsys.com>
Diffstat (limited to 'drivers/pci/dwc')
-rw-r--r--drivers/pci/dwc/pcie-designware-host.c36
1 files changed, 22 insertions, 14 deletions
diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
index 28ed32ba4f1b..351a277c89d9 100644
--- a/drivers/pci/dwc/pcie-designware-host.c
+++ b/drivers/pci/dwc/pcie-designware-host.c
@@ -280,9 +280,9 @@ int dw_pcie_host_init(struct pcie_port *pp)
struct device_node *np = dev->of_node;
struct platform_device *pdev = to_platform_device(dev);
struct pci_bus *bus, *child;
+ struct pci_host_bridge *bridge;
struct resource *cfg_res;
int i, ret;
- LIST_HEAD(res);
struct resource_entry *win, *tmp;
cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
@@ -295,16 +295,21 @@ int dw_pcie_host_init(struct pcie_port *pp)
dev_err(dev, "missing *config* reg space\n");
}
- ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base);
+ bridge = pci_alloc_host_bridge(0);
+ if (!bridge)
+ return -ENOMEM;
+
+ ret = of_pci_get_host_bridge_resources(np, 0, 0xff,
+ &bridge->windows, &pp->io_base);
if (ret)
return ret;
- ret = devm_request_pci_bus_resources(dev, &res);
+ ret = devm_request_pci_bus_resources(dev, &bridge->windows);
if (ret)
goto error;
/* Get the I/O and memory ranges from DT */
- resource_list_for_each_entry_safe(win, tmp, &res) {
+ resource_list_for_each_entry_safe(win, tmp, &bridge->windows) {
switch (resource_type(win->res)) {
case IORESOURCE_IO:
ret = pci_remap_iospace(win->res, pp->io_base);
@@ -400,19 +405,22 @@ int dw_pcie_host_init(struct pcie_port *pp)
pp->ops->host_init(pp);
pp->root_bus_nr = pp->busn->start;
+
+ bridge->dev.parent = dev;
+ bridge->sysdata = pp;
+ bridge->busnr = pp->root_bus_nr;
+ bridge->ops = &dw_pcie_ops;
if (IS_ENABLED(CONFIG_PCI_MSI)) {
- bus = pci_scan_root_bus_msi(dev, pp->root_bus_nr,
- &dw_pcie_ops, pp, &res,
- &dw_pcie_msi_chip);
+ bridge->msi = &dw_pcie_msi_chip;
dw_pcie_msi_chip.dev = dev;
- } else
- bus = pci_scan_root_bus(dev, pp->root_bus_nr, &dw_pcie_ops,
- pp, &res);
- if (!bus) {
- ret = -ENOMEM;
- goto error;
}
+ ret = pci_scan_root_bus_bridge(bridge);
+ if (ret)
+ goto error;
+
+ bus = bridge->bus;
+
if (pp->ops->scan_bus)
pp->ops->scan_bus(pp);
@@ -431,7 +439,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
return 0;
error:
- pci_free_resource_list(&res);
+ pci_free_host_bridge(bridge);
return ret;
}