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| author | Kishon Vijay Abraham I <kishon@ti.com> | 2017-02-15 18:48:14 +0530 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2017-02-21 15:00:26 -0600 |
| commit | 442ec4c04d1235f8c664a74004dae54a7a574d18 (patch) | |
| tree | 66e1b54e8cabd635a378b48307175dac998fa47b /drivers/pci/dwc/pci-keystone.h | |
| parent | 40f67fb2c384fe12741aa35010d62bfe8c98286c (diff) | |
| download | lwn-442ec4c04d1235f8c664a74004dae54a7a574d18.tar.gz lwn-442ec4c04d1235f8c664a74004dae54a7a574d18.zip | |
PCI: dwc: all: Split struct pcie_port into host-only and core structures
Keep only the host-specific members in struct pcie_port and move the common
members (i.e common to both host and endpoint) to struct dw_pcie. This is
in preparation for adding endpoint mode support to designware driver.
While at that also fix checkpatch warnings.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: Jingoo Han <jingoohan1@gmail.com>
CC: Richard Zhu <hongxing.zhu@nxp.com>
CC: Lucas Stach <l.stach@pengutronix.de>
CC: Murali Karicheri <m-karicheri2@ti.com>
CC: Minghuan Lian <minghuan.Lian@freescale.com>
CC: Mingkai Hu <mingkai.hu@freescale.com>
CC: Roy Zang <tie-fei.zang@freescale.com>
CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
CC: Niklas Cassel <niklas.cassel@axis.com>
CC: Jesper Nilsson <jesper.nilsson@axis.com>
CC: Joao Pinto <Joao.Pinto@synopsys.com>
CC: Zhou Wang <wangzhou1@hisilicon.com>
CC: Gabriele Paoloni <gabriele.paoloni@huawei.com>
CC: Stanimir Varbanov <svarbanov@mm-sol.com>
CC: Pratyush Anand <pratyush.anand@gmail.com>
Diffstat (limited to 'drivers/pci/dwc/pci-keystone.h')
| -rw-r--r-- | drivers/pci/dwc/pci-keystone.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pci/dwc/pci-keystone.h b/drivers/pci/dwc/pci-keystone.h index bc54bafda068..74c5825882df 100644 --- a/drivers/pci/dwc/pci-keystone.h +++ b/drivers/pci/dwc/pci-keystone.h @@ -17,7 +17,7 @@ #define MAX_LEGACY_HOST_IRQS 4 struct keystone_pcie { - struct pcie_port pp; /* pp.dbi_base is DT 0th res */ + struct dw_pcie *pci; struct clk *clk; /* PCI Device ID */ u32 device_id; @@ -54,10 +54,10 @@ int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie); -int ks_dw_pcie_link_up(struct pcie_port *pp); void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie); void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq); void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq); void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp); int ks_dw_pcie_msi_host_init(struct pcie_port *pp, struct msi_controller *chip); +int ks_dw_pcie_link_up(struct dw_pcie *pci); |