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| author | Bjorn Helgaas <bhelgaas@google.com> | 2024-07-19 10:10:32 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2024-07-19 10:10:32 -0500 |
| commit | 8240a9b4a5a27ce20a0ae2dea2b2e830be34f3b9 (patch) | |
| tree | 2e38c765162174053f62e53c9c5aba39be031960 /drivers/pci/controller/pcie-rockchip-host.c | |
| parent | 59dd7046b4fbe60d74544f8a77c63899ce8b3618 (diff) | |
| parent | 84e30b878aed9353d74904d72cba9f968ae5675b (diff) | |
| download | lwn-8240a9b4a5a27ce20a0ae2dea2b2e830be34f3b9.tar.gz lwn-8240a9b4a5a27ce20a0ae2dea2b2e830be34f3b9.zip | |
Merge branch 'pci/controller/rockchip'
- Use dev_err_probe() in dw-rockchip probe error path so the failures
aren't silent (Uwe Kleine-König)
- Sleep PCIE_T_PVPERL_MS (100ms) before deasserting PERST# (Damien Le Moal)
- Sleep PCIE_T_RRS_READY_MS (100ms) after conventional reset, before a
config access (Damien Le Moal)
- Request the PERST# GPIO with GPIOD_OUT_LOW so it matches the POR value,
which avoids a spurious PERST# assertion and fixes a Qcom modem firmware
crash and issues with WLAN controllers, e.g., RTL8822CE (Manivannan
Sadhasivam for rockchip, Niklas Cassel for dw-rockchip)
- Refactor dw-rockchip and add support for Endpoint mode for rk3568 and
rk3588 (Niklas Cassel)
* pci/controller/rockchip:
PCI: dw-rockchip: Use pci_epc_init_notify() directly
PCI: dw-rockchip: Add endpoint mode support
PCI: dw-rockchip: Refactor the driver to prepare for EP mode
PCI: dw-rockchip: Add rockchip_pcie_get_ltssm() helper
PCI: dw-rockchip: Fix weird indentation
PCI: dw-rockchip: Fix initial PERST# GPIO value
PCI: dw-rockchip: Add error messages in .probe() error paths
PCI: rockchip: Use GPIOD_OUT_LOW flag while requesting ep_gpio
PCI: rockchip-host: Wait 100ms after reset before starting configuration
PCI: rockchip-host: Fix rockchip_pcie_host_init_port() PERST# handling
Diffstat (limited to 'drivers/pci/controller/pcie-rockchip-host.c')
| -rw-r--r-- | drivers/pci/controller/pcie-rockchip-host.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c index 300b9dc85ecc..cbec71114825 100644 --- a/drivers/pci/controller/pcie-rockchip-host.c +++ b/drivers/pci/controller/pcie-rockchip-host.c @@ -322,8 +322,11 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip) rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, PCIE_CLIENT_CONFIG); + msleep(PCIE_T_PVPERL_MS); gpiod_set_value_cansleep(rockchip->ep_gpio, 1); + msleep(PCIE_T_RRS_READY_MS); + /* 500ms timeout value should be enough for Gen1/2 training */ err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1, status, PCIE_LINK_UP(status), 20, |