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authorGustavo Pimentel <gustavo.pimentel@synopsys.com>2019-01-31 19:17:07 +0100
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2019-02-01 12:36:36 +0000
commit657722570a555c728c59f17f7825c812c124dc28 (patch)
treea6c8f6f3420f420e7f78d8b9e815437a4e2b30d7 /drivers/pci/controller/dwc/pcie-designware-host.c
parenta348d015f0de7a08f88f8089f6f6c4bc5248029b (diff)
downloadlwn-657722570a555c728c59f17f7825c812c124dc28.tar.gz
lwn-657722570a555c728c59f17f7825c812c124dc28.zip
PCI: dwc: Replace bit rotation operation (1 << bit) with BIT(bit)
Replace bit rotation operation (1 << bit) with BIT(bit), which simplifies code reading. No functional change is intended. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Joao Pinto <jpinto@synopsys.com> Cc: Jingoo Han <jingoohan1@gmail.com>
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-designware-host.c')
-rw-r--r--drivers/pci/controller/dwc/pcie-designware-host.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index c550c4a7ef89..45ff5e4f8af6 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -164,7 +164,7 @@ static void dw_pci_bottom_mask(struct irq_data *d)
res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
- pp->irq_mask[ctrl] |= (1 << bit);
+ pp->irq_mask[ctrl] |= BIT(bit);
dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
pp->irq_mask[ctrl]);
}
@@ -187,7 +187,7 @@ static void dw_pci_bottom_unmask(struct irq_data *d)
res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
- pp->irq_mask[ctrl] &= ~(1 << bit);
+ pp->irq_mask[ctrl] &= ~BIT(bit);
dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
pp->irq_mask[ctrl]);
}
@@ -207,7 +207,7 @@ static void dw_pci_bottom_ack(struct irq_data *d)
raw_spin_lock_irqsave(&pp->lock, flags);
- dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + res, 4, 1 << bit);
+ dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + res, 4, BIT(bit));
if (pp->ops->msi_irq_ack)
pp->ops->msi_irq_ack(d->hwirq, pp);