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| author | Dong Aisheng <b29396@freescale.com> | 2014-10-29 18:45:24 +0800 |
|---|---|---|
| committer | Marc Kleine-Budde <mkl@pengutronix.de> | 2014-11-18 21:35:05 +0100 |
| commit | 7660f633070986ab4ee41c063a90e140d5781e13 (patch) | |
| tree | f28d7b59ee88fac428a96e2e321727de42b2185b /drivers/net | |
| parent | 921f168109d029e3b59459c3a2754f0e2a70fad3 (diff) | |
| download | lwn-7660f633070986ab4ee41c063a90e140d5781e13.tar.gz lwn-7660f633070986ab4ee41c063a90e140d5781e13.zip | |
can: m_can: add missing delay after setting CCCR_INIT bit
The spec mentions there may be a delay until the value written to INIT can be
read back due to the synchronization mechanism between the two clock domains.
But it does not indicate the exact clock cycles needed. The 5us delay is a
test value and seems ok.
Without the delay, CCCR.CCE bit may fail to be set and then the initialization
fail sometimes when do repeatly up and down.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/can/m_can/m_can.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c index 98f7e0ea7f6a..3ad7d88720b7 100644 --- a/drivers/net/can/m_can/m_can.c +++ b/drivers/net/can/m_can/m_can.c @@ -296,6 +296,7 @@ static inline void m_can_config_endisable(const struct m_can_priv *priv, if (enable) { /* enable m_can configuration */ m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT); + udelay(5); /* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */ m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE); } else { |