diff options
| author | Helmut Schaa <helmut.schaa@googlemail.com> | 2010-12-13 12:33:36 +0100 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2010-12-13 15:23:34 -0500 |
| commit | 89b25f60e08180d7e00e6239398b467142aaec01 (patch) | |
| tree | 7c8dd38055d85a9b062b524353835ad162a02a69 /drivers/net/wireless/rt2x00/rt2400pci.c | |
| parent | a061a93b6eb8db8227b251666436da1e344771a0 (diff) | |
| download | lwn-89b25f60e08180d7e00e6239398b467142aaec01.tar.gz lwn-89b25f60e08180d7e00e6239398b467142aaec01.zip | |
rt2x00: Don't frequently reset beacon interval in AdHoc mode
Commit 0204464329c17ba6d293e1899f71223599a0e582 "Check for specific changed
flags when updating the erp config" changed the way in which a new beacon
interval gets handled. However, due to a bug in rt2800usb and rt2800pci the
beacon interval was reset during each scan, thus causing problems in AdHoc
mode.
Fix this by not cleaning up the beacon interval when killing the beacon queue
but just prevent the device from sending out beacons.
Reported-by: Wolfgang Kufner <wolfgang.kufner@gmail.com>
Signed-off-by: Helmut Schaa <helmut.schaa@googlemail.com>
Acked-by: Gertjan van Wingerde <gwingerde@gmail.com>
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2400pci.c')
| -rw-r--r-- | drivers/net/wireless/rt2x00/rt2400pci.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2400pci.c b/drivers/net/wireless/rt2x00/rt2400pci.c index 9ec6691adf0d..62786608951e 100644 --- a/drivers/net/wireless/rt2x00/rt2400pci.c +++ b/drivers/net/wireless/rt2x00/rt2400pci.c @@ -1140,7 +1140,11 @@ static void rt2400pci_kill_tx_queue(struct data_queue *queue) u32 reg; if (queue->qid == QID_BEACON) { - rt2x00pci_register_write(rt2x00dev, CSR14, 0); + rt2x00pci_register_read(rt2x00dev, CSR14, ®); + rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); + rt2x00_set_field32(®, CSR14_TBCN, 0); + rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); + rt2x00pci_register_write(rt2x00dev, CSR14, reg); } else { rt2x00pci_register_read(rt2x00dev, TXCSR0, ®); rt2x00_set_field32(®, TXCSR0_ABORT, 1); |