diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2017-07-05 12:31:59 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2017-07-05 12:31:59 -0700 |
| commit | 5518b69b76680a4f2df96b1deca260059db0c2de (patch) | |
| tree | f33cd1519c8efb4590500f2f9617400be233238c /drivers/net/wireless/ralink/rt2x00/rt61pci.c | |
| parent | 8ad06e56dcbc1984ef0ff8f6e3c19982c5809f73 (diff) | |
| parent | 0e72582270c07850b92cac351c8b97d4f9c123b9 (diff) | |
| download | lwn-5518b69b76680a4f2df96b1deca260059db0c2de.tar.gz lwn-5518b69b76680a4f2df96b1deca260059db0c2de.zip | |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next
Pull networking updates from David Miller:
"Reasonably busy this cycle, but perhaps not as busy as in the 4.12
merge window:
1) Several optimizations for UDP processing under high load from
Paolo Abeni.
2) Support pacing internally in TCP when using the sch_fq packet
scheduler for this is not practical. From Eric Dumazet.
3) Support mutliple filter chains per qdisc, from Jiri Pirko.
4) Move to 1ms TCP timestamp clock, from Eric Dumazet.
5) Add batch dequeueing to vhost_net, from Jason Wang.
6) Flesh out more completely SCTP checksum offload support, from
Davide Caratti.
7) More plumbing of extended netlink ACKs, from David Ahern, Pablo
Neira Ayuso, and Matthias Schiffer.
8) Add devlink support to nfp driver, from Simon Horman.
9) Add RTM_F_FIB_MATCH flag to RTM_GETROUTE queries, from Roopa
Prabhu.
10) Add stack depth tracking to BPF verifier and use this information
in the various eBPF JITs. From Alexei Starovoitov.
11) Support XDP on qed device VFs, from Yuval Mintz.
12) Introduce BPF PROG ID for better introspection of installed BPF
programs. From Martin KaFai Lau.
13) Add bpf_set_hash helper for TC bpf programs, from Daniel Borkmann.
14) For loads, allow narrower accesses in bpf verifier checking, from
Yonghong Song.
15) Support MIPS in the BPF selftests and samples infrastructure, the
MIPS eBPF JIT will be merged in via the MIPS GIT tree. From David
Daney.
16) Support kernel based TLS, from Dave Watson and others.
17) Remove completely DST garbage collection, from Wei Wang.
18) Allow installing TCP MD5 rules using prefixes, from Ivan
Delalande.
19) Add XDP support to Intel i40e driver, from Björn Töpel
20) Add support for TC flower offload in nfp driver, from Simon
Horman, Pieter Jansen van Vuuren, Benjamin LaHaise, Jakub
Kicinski, and Bert van Leeuwen.
21) IPSEC offloading support in mlx5, from Ilan Tayari.
22) Add HW PTP support to macb driver, from Rafal Ozieblo.
23) Networking refcount_t conversions, From Elena Reshetova.
24) Add sock_ops support to BPF, from Lawrence Brako. This is useful
for tuning the TCP sockopt settings of a group of applications,
currently via CGROUPs"
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1899 commits)
net: phy: dp83867: add workaround for incorrect RX_CTRL pin strap
dt-bindings: phy: dp83867: provide a workaround for incorrect RX_CTRL pin strap
cxgb4: Support for get_ts_info ethtool method
cxgb4: Add PTP Hardware Clock (PHC) support
cxgb4: time stamping interface for PTP
nfp: default to chained metadata prepend format
nfp: remove legacy MAC address lookup
nfp: improve order of interfaces in breakout mode
net: macb: remove extraneous return when MACB_EXT_DESC is defined
bpf: add missing break in for the TCP_BPF_SNDCWND_CLAMP case
bpf: fix return in load_bpf_file
mpls: fix rtm policy in mpls_getroute
net, ax25: convert ax25_cb.refcount from atomic_t to refcount_t
net, ax25: convert ax25_route.refcount from atomic_t to refcount_t
net, ax25: convert ax25_uid_assoc.refcount from atomic_t to refcount_t
net, sctp: convert sctp_ep_common.refcnt from atomic_t to refcount_t
net, sctp: convert sctp_transport.refcnt from atomic_t to refcount_t
net, sctp: convert sctp_chunk.refcnt from atomic_t to refcount_t
net, sctp: convert sctp_datamsg.refcnt from atomic_t to refcount_t
net, sctp: convert sctp_auth_bytes.refcnt from atomic_t to refcount_t
...
Diffstat (limited to 'drivers/net/wireless/ralink/rt2x00/rt61pci.c')
| -rw-r--r-- | drivers/net/wireless/ralink/rt2x00/rt61pci.c | 285 |
1 files changed, 144 insertions, 141 deletions
diff --git a/drivers/net/wireless/ralink/rt2x00/rt61pci.c b/drivers/net/wireless/ralink/rt2x00/rt61pci.c index 973d418b8113..234310200759 100644 --- a/drivers/net/wireless/ralink/rt2x00/rt61pci.c +++ b/drivers/net/wireless/ralink/rt2x00/rt61pci.c @@ -86,10 +86,11 @@ static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev, mutex_unlock(&rt2x00dev->csr_mutex); } -static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev, - const unsigned int word, u8 *value) +static u8 rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev, + const unsigned int word) { u32 reg; + u8 value; mutex_lock(&rt2x00dev->csr_mutex); @@ -112,9 +113,11 @@ static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev, WAIT_FOR_BBP(rt2x00dev, ®); } - *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE); + value = rt2x00_get_field32(reg, PHY_CSR3_VALUE); mutex_unlock(&rt2x00dev->csr_mutex); + + return value; } static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev, @@ -161,7 +164,7 @@ static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev, rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg); - rt2x00mmio_register_read(rt2x00dev, HOST_CMD_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, HOST_CMD_CSR); rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); rt2x00_set_field32(®, HOST_CMD_CSR_INTERRUPT_MCU, 1); rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, reg); @@ -176,7 +179,7 @@ static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom) struct rt2x00_dev *rt2x00dev = eeprom->data; u32 reg; - rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR); eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN); eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT); @@ -240,7 +243,7 @@ static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev) { u32 reg; - rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, ®); + reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR13); return rt2x00_get_field32(reg, MAC_CSR13_VAL5); } @@ -291,7 +294,7 @@ static int rt61pci_blink_set(struct led_classdev *led_cdev, container_of(led_cdev, struct rt2x00_led, led_dev); u32 reg; - rt2x00mmio_register_read(led->rt2x00dev, MAC_CSR14, ®); + reg = rt2x00mmio_register_read(led->rt2x00dev, MAC_CSR14); rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, *delay_on); rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, *delay_off); rt2x00mmio_register_write(led->rt2x00dev, MAC_CSR14, reg); @@ -336,7 +339,7 @@ static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev, */ mask = (0xf << crypto->bssidx); - rt2x00mmio_register_read(rt2x00dev, SEC_CSR0, ®); + reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR0); reg &= mask; if (reg && reg == mask) @@ -369,14 +372,14 @@ static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev, field.bit_offset = (3 * key->hw_key_idx); field.bit_mask = 0x7 << field.bit_offset; - rt2x00mmio_register_read(rt2x00dev, SEC_CSR1, ®); + reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR1); rt2x00_set_field32(®, field, crypto->cipher); rt2x00mmio_register_write(rt2x00dev, SEC_CSR1, reg); } else { field.bit_offset = (3 * (key->hw_key_idx - 8)); field.bit_mask = 0x7 << field.bit_offset; - rt2x00mmio_register_read(rt2x00dev, SEC_CSR5, ®); + reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR5); rt2x00_set_field32(®, field, crypto->cipher); rt2x00mmio_register_write(rt2x00dev, SEC_CSR5, reg); } @@ -401,7 +404,7 @@ static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev, */ mask = 1 << key->hw_key_idx; - rt2x00mmio_register_read(rt2x00dev, SEC_CSR0, ®); + reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR0); if (crypto->cmd == SET_KEY) reg |= mask; else if (crypto->cmd == DISABLE_KEY) @@ -430,10 +433,10 @@ static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev, * When both registers are full, we drop the key. * Otherwise, we use the first invalid entry. */ - rt2x00mmio_register_read(rt2x00dev, SEC_CSR2, ®); + reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR2); if (reg && reg == ~0) { key->hw_key_idx = 32; - rt2x00mmio_register_read(rt2x00dev, SEC_CSR3, ®); + reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR3); if (reg && reg == ~0) return -ENOSPC; } @@ -467,7 +470,7 @@ static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev, * Without this, received frames will not be decrypted * by the hardware. */ - rt2x00mmio_register_read(rt2x00dev, SEC_CSR4, ®); + reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR4); reg |= (1 << crypto->bssidx); rt2x00mmio_register_write(rt2x00dev, SEC_CSR4, reg); @@ -492,7 +495,7 @@ static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev, if (key->hw_key_idx < 32) { mask = 1 << key->hw_key_idx; - rt2x00mmio_register_read(rt2x00dev, SEC_CSR2, ®); + reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR2); if (crypto->cmd == SET_KEY) reg |= mask; else if (crypto->cmd == DISABLE_KEY) @@ -501,7 +504,7 @@ static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev, } else { mask = 1 << (key->hw_key_idx - 32); - rt2x00mmio_register_read(rt2x00dev, SEC_CSR3, ®); + reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR3); if (crypto->cmd == SET_KEY) reg |= mask; else if (crypto->cmd == DISABLE_KEY) @@ -523,7 +526,7 @@ static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev, * and broadcast frames will always be accepted since * there is no filter for it at this time. */ - rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC, !(filter_flags & FIF_FCSFAIL)); rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL, @@ -555,7 +558,7 @@ static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev, /* * Enable synchronisation. */ - rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync); rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); } @@ -586,13 +589,13 @@ static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev, { u32 reg; - rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32); rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); if (changed & BSS_CHANGED_ERP_PREAMBLE) { - rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4); rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1); rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE, !!erp->short_preamble); @@ -604,18 +607,18 @@ static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev, erp->basic_rates); if (changed & BSS_CHANGED_BEACON_INT) { - rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, erp->beacon_int * 16); rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); } if (changed & BSS_CHANGED_ERP_SLOT) { - rt2x00mmio_register_read(rt2x00dev, MAC_CSR9, ®); + reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR9); rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, erp->slot_time); rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg); - rt2x00mmio_register_read(rt2x00dev, MAC_CSR8, ®); + reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR8); rt2x00_set_field32(®, MAC_CSR8_SIFS, erp->sifs); rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); rt2x00_set_field32(®, MAC_CSR8_EIFS, erp->eifs); @@ -630,9 +633,9 @@ static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev, u8 r4; u8 r77; - rt61pci_bbp_read(rt2x00dev, 3, &r3); - rt61pci_bbp_read(rt2x00dev, 4, &r4); - rt61pci_bbp_read(rt2x00dev, 77, &r77); + r3 = rt61pci_bbp_read(rt2x00dev, 3); + r4 = rt61pci_bbp_read(rt2x00dev, 4); + r77 = rt61pci_bbp_read(rt2x00dev, 77); rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325)); @@ -676,9 +679,9 @@ static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev, u8 r4; u8 r77; - rt61pci_bbp_read(rt2x00dev, 3, &r3); - rt61pci_bbp_read(rt2x00dev, 4, &r4); - rt61pci_bbp_read(rt2x00dev, 77, &r77); + r3 = rt61pci_bbp_read(rt2x00dev, 3); + r4 = rt61pci_bbp_read(rt2x00dev, 4); + r77 = rt61pci_bbp_read(rt2x00dev, 77); rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529)); rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, @@ -712,7 +715,7 @@ static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev, { u32 reg; - rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, ®); + reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR13); rt2x00_set_field32(®, MAC_CSR13_DIR4, 0); rt2x00_set_field32(®, MAC_CSR13_VAL4, p1); @@ -730,9 +733,9 @@ static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev, u8 r4; u8 r77; - rt61pci_bbp_read(rt2x00dev, 3, &r3); - rt61pci_bbp_read(rt2x00dev, 4, &r4); - rt61pci_bbp_read(rt2x00dev, 77, &r77); + r3 = rt61pci_bbp_read(rt2x00dev, 3); + r4 = rt61pci_bbp_read(rt2x00dev, 4); + r77 = rt61pci_bbp_read(rt2x00dev, 77); /* * Configure the RX antenna. @@ -819,7 +822,7 @@ static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev, for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++) rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]); - rt2x00mmio_register_read(rt2x00dev, PHY_CSR0, ®); + reg = rt2x00mmio_register_read(rt2x00dev, PHY_CSR0); rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, rt2x00dev->curr_band == NL80211_BAND_2GHZ); @@ -850,13 +853,13 @@ static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev, if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) lna_gain += 14; - rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom); + eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG); lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1); } else { if (rt2x00_has_cap_external_lna_a(rt2x00dev)) lna_gain += 14; - rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom); + eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A); lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1); } @@ -875,7 +878,7 @@ static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev, smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527)); - rt61pci_bbp_read(rt2x00dev, 3, &r3); + r3 = rt61pci_bbp_read(rt2x00dev, 3); rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart); rt61pci_bbp_write(rt2x00dev, 3, r3); @@ -913,10 +916,10 @@ static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev, { struct rf_channel rf; - rt2x00_rf_read(rt2x00dev, 1, &rf.rf1); - rt2x00_rf_read(rt2x00dev, 2, &rf.rf2); - rt2x00_rf_read(rt2x00dev, 3, &rf.rf3); - rt2x00_rf_read(rt2x00dev, 4, &rf.rf4); + rf.rf1 = rt2x00_rf_read(rt2x00dev, 1); + rf.rf2 = rt2x00_rf_read(rt2x00dev, 2); + rf.rf3 = rt2x00_rf_read(rt2x00dev, 3); + rf.rf4 = rt2x00_rf_read(rt2x00dev, 4); rt61pci_config_channel(rt2x00dev, &rf, txpower); } @@ -926,7 +929,7 @@ static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev, { u32 reg; - rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4); rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1); rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_STEP, 0); rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0); @@ -946,7 +949,7 @@ static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev, u32 reg; if (state == STATE_SLEEP) { - rt2x00mmio_register_read(rt2x00dev, MAC_CSR11, ®); + reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR11); rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, rt2x00dev->beacon_int - 10); rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, @@ -967,7 +970,7 @@ static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev, rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0); } else { - rt2x00mmio_register_read(rt2x00dev, MAC_CSR11, ®); + reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR11); rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, 0); rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0); rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); @@ -1013,13 +1016,13 @@ static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev, /* * Update FCS error count from register. */ - rt2x00mmio_register_read(rt2x00dev, STA_CSR0, ®); + reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR0); qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR); /* * Update False CCA count from register. */ - rt2x00mmio_register_read(rt2x00dev, STA_CSR1, ®); + reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR1); qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR); } @@ -1138,12 +1141,12 @@ static void rt61pci_start_queue(struct data_queue *queue) switch (queue->qid) { case QID_RX: - rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); break; case QID_BEACON: - rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1); rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1); rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); @@ -1161,22 +1164,22 @@ static void rt61pci_kick_queue(struct data_queue *queue) switch (queue->qid) { case QID_AC_VO: - rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, 1); rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); break; case QID_AC_VI: - rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, 1); rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); break; case QID_AC_BE: - rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, 1); rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); break; case QID_AC_BK: - rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, 1); rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); break; @@ -1192,32 +1195,32 @@ static void rt61pci_stop_queue(struct data_queue *queue) switch (queue->qid) { case QID_AC_VO: - rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, 1); rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); break; case QID_AC_VI: - rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, 1); rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); break; case QID_AC_BE: - rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, 1); rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); break; case QID_AC_BK: - rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, 1); rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); break; case QID_RX: - rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 1); rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); break; case QID_BEACON: - rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); @@ -1299,7 +1302,7 @@ static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, * Wait for stable hardware. */ for (i = 0; i < 100; i++) { - rt2x00mmio_register_read(rt2x00dev, MAC_CSR0, ®); + reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR0); if (reg) break; msleep(1); @@ -1338,7 +1341,7 @@ static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); for (i = 0; i < 100; i++) { - rt2x00mmio_register_read(rt2x00dev, MCU_CNTL_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, MCU_CNTL_CSR); if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY)) break; msleep(1); @@ -1362,12 +1365,12 @@ static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); - rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); + reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); - rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); + reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); @@ -1383,11 +1386,11 @@ static bool rt61pci_get_entry_state(struct queue_entry *entry) u32 word; if (entry->queue->qid == QID_RX) { - rt2x00_desc_read(entry_priv->desc, 0, &word); + word = rt2x00_desc_read(entry_priv->desc, 0); return rt2x00_get_field32(word, RXD_W0_OWNER_NIC); } else { - rt2x00_desc_read(entry_priv->desc, 0, &word); + word = rt2x00_desc_read(entry_priv->desc, 0); return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || rt2x00_get_field32(word, TXD_W0_VALID)); @@ -1401,16 +1404,16 @@ static void rt61pci_clear_entry(struct queue_entry *entry) u32 word; if (entry->queue->qid == QID_RX) { - rt2x00_desc_read(entry_priv->desc, 5, &word); + word = rt2x00_desc_read(entry_priv->desc, 5); rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS, skbdesc->skb_dma); rt2x00_desc_write(entry_priv->desc, 5, word); - rt2x00_desc_read(entry_priv->desc, 0, &word); + word = rt2x00_desc_read(entry_priv->desc, 0); rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); rt2x00_desc_write(entry_priv->desc, 0, word); } else { - rt2x00_desc_read(entry_priv->desc, 0, &word); + word = rt2x00_desc_read(entry_priv->desc, 0); rt2x00_set_field32(&word, TXD_W0_VALID, 0); rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); rt2x00_desc_write(entry_priv->desc, 0, word); @@ -1425,7 +1428,7 @@ static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev) /* * Initialize registers. */ - rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR0, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR0); rt2x00_set_field32(®, TX_RING_CSR0_AC0_RING_SIZE, rt2x00dev->tx[0].limit); rt2x00_set_field32(®, TX_RING_CSR0_AC1_RING_SIZE, @@ -1436,36 +1439,36 @@ static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev) rt2x00dev->tx[3].limit); rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR0, reg); - rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR1, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR1); rt2x00_set_field32(®, TX_RING_CSR1_TXD_SIZE, rt2x00dev->tx[0].desc_size / 4); rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR1, reg); entry_priv = rt2x00dev->tx[0].entries[0].priv_data; - rt2x00mmio_register_read(rt2x00dev, AC0_BASE_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, AC0_BASE_CSR); rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER, entry_priv->desc_dma); rt2x00mmio_register_write(rt2x00dev, AC0_BASE_CSR, reg); entry_priv = rt2x00dev->tx[1].entries[0].priv_data; - rt2x00mmio_register_read(rt2x00dev, AC1_BASE_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, AC1_BASE_CSR); rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER, entry_priv->desc_dma); rt2x00mmio_register_write(rt2x00dev, AC1_BASE_CSR, reg); entry_priv = rt2x00dev->tx[2].entries[0].priv_data; - rt2x00mmio_register_read(rt2x00dev, AC2_BASE_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, AC2_BASE_CSR); rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER, entry_priv->desc_dma); rt2x00mmio_register_write(rt2x00dev, AC2_BASE_CSR, reg); entry_priv = rt2x00dev->tx[3].entries[0].priv_data; - rt2x00mmio_register_read(rt2x00dev, AC3_BASE_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, AC3_BASE_CSR); rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER, entry_priv->desc_dma); rt2x00mmio_register_write(rt2x00dev, AC3_BASE_CSR, reg); - rt2x00mmio_register_read(rt2x00dev, RX_RING_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, RX_RING_CSR); rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit); rt2x00_set_field32(®, RX_RING_CSR_RXD_SIZE, rt2x00dev->rx->desc_size / 4); @@ -1473,26 +1476,26 @@ static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev) rt2x00mmio_register_write(rt2x00dev, RX_RING_CSR, reg); entry_priv = rt2x00dev->rx->entries[0].priv_data; - rt2x00mmio_register_read(rt2x00dev, RX_BASE_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, RX_BASE_CSR); rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER, entry_priv->desc_dma); rt2x00mmio_register_write(rt2x00dev, RX_BASE_CSR, reg); - rt2x00mmio_register_read(rt2x00dev, TX_DMA_DST_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TX_DMA_DST_CSR); rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC0, 2); rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC1, 2); rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC2, 2); rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC3, 2); rt2x00mmio_register_write(rt2x00dev, TX_DMA_DST_CSR, reg); - rt2x00mmio_register_read(rt2x00dev, LOAD_TX_RING_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, LOAD_TX_RING_CSR); rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1); rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1); rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1); rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1); rt2x00mmio_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg); - rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR); rt2x00_set_field32(®, RX_CNTL_CSR_LOAD_RXD, 1); rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg); @@ -1503,13 +1506,13 @@ static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev) { u32 reg; - rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1); rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0); rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); - rt2x00mmio_register_read(rt2x00dev, TXRX_CSR1, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR1); rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */ rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1); rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */ @@ -1523,7 +1526,7 @@ static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev) /* * CCK TXD BBP registers */ - rt2x00mmio_register_read(rt2x00dev, TXRX_CSR2, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR2); rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13); rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1); rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12); @@ -1537,7 +1540,7 @@ static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev) /* * OFDM TXD BBP registers */ - rt2x00mmio_register_read(rt2x00dev, TXRX_CSR3, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR3); rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7); rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1); rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6); @@ -1546,21 +1549,21 @@ static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev) rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1); rt2x00mmio_register_write(rt2x00dev, TXRX_CSR3, reg); - rt2x00mmio_register_read(rt2x00dev, TXRX_CSR7, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR7); rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59); rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53); rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49); rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46); rt2x00mmio_register_write(rt2x00dev, TXRX_CSR7, reg); - rt2x00mmio_register_read(rt2x00dev, TXRX_CSR8, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR8); rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44); rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42); rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42); rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42); rt2x00mmio_register_write(rt2x00dev, TXRX_CSR8, reg); - rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 0); rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0); @@ -1573,7 +1576,7 @@ static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev) rt2x00mmio_register_write(rt2x00dev, MAC_CSR6, 0x00000fff); - rt2x00mmio_register_read(rt2x00dev, MAC_CSR9, ®); + reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR9); rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0); rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg); @@ -1619,24 +1622,24 @@ static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev) * These registers are cleared on read, * so we may pass a useless variable to store the value. */ - rt2x00mmio_register_read(rt2x00dev, STA_CSR0, ®); - rt2x00mmio_register_read(rt2x00dev, STA_CSR1, ®); - rt2x00mmio_register_read(rt2x00dev, STA_CSR2, ®); + reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR0); + reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR1); + reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR2); /* * Reset MAC and BBP registers. */ - rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); + reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); - rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); + reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); - rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); + reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); @@ -1649,7 +1652,7 @@ static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) u8 value; for (i = 0; i < REGISTER_BUSY_COUNT; i++) { - rt61pci_bbp_read(rt2x00dev, 0, &value); + value = rt61pci_bbp_read(rt2x00dev, 0); if ((value != 0xff) && (value != 0x00)) return 0; udelay(REGISTER_BUSY_DELAY); @@ -1695,7 +1698,7 @@ static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev) rt61pci_bbp_write(rt2x00dev, 107, 0x04); for (i = 0; i < EEPROM_BBP_SIZE; i++) { - rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); + eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i); if (eeprom != 0xffff && eeprom != 0x0000) { reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); @@ -1722,10 +1725,10 @@ static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev, * should clear the register to assure a clean state. */ if (state == STATE_RADIO_IRQ_ON) { - rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR); rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); - rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR); rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg); } @@ -1735,7 +1738,7 @@ static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev, */ spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags); - rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); rt2x00_set_field32(®, INT_MASK_CSR_TXDONE, mask); rt2x00_set_field32(®, INT_MASK_CSR_RXDONE, mask); rt2x00_set_field32(®, INT_MASK_CSR_BEACON_DONE, mask); @@ -1743,7 +1746,7 @@ static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev, rt2x00_set_field32(®, INT_MASK_CSR_MITIGATION_PERIOD, 0xff); rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); - rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR); rt2x00_set_field32(®, MCU_INT_MASK_CSR_0, mask); rt2x00_set_field32(®, MCU_INT_MASK_CSR_1, mask); rt2x00_set_field32(®, MCU_INT_MASK_CSR_2, mask); @@ -1783,7 +1786,7 @@ static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev) /* * Enable RX. */ - rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR); rt2x00_set_field32(®, RX_CNTL_CSR_ENABLE_RX_DMA, 1); rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg); @@ -1806,7 +1809,7 @@ static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) put_to_sleep = (state != STATE_AWAKE); - rt2x00mmio_register_read(rt2x00dev, MAC_CSR12, ®); + reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR12); rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep); rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep); rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg); @@ -1817,7 +1820,7 @@ static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) * device has entered the correct state. */ for (i = 0; i < REGISTER_BUSY_COUNT; i++) { - rt2x00mmio_register_read(rt2x00dev, MAC_CSR12, ®2); + reg2 = rt2x00mmio_register_read(rt2x00dev, MAC_CSR12); state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE); if (state == !put_to_sleep) return 0; @@ -1876,7 +1879,7 @@ static void rt61pci_write_tx_desc(struct queue_entry *entry, /* * Start writing the descriptor words. */ - rt2x00_desc_read(txd, 1, &word); + word = rt2x00_desc_read(txd, 1); rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid); rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs); rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min); @@ -1887,7 +1890,7 @@ static void rt61pci_write_tx_desc(struct queue_entry *entry, rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1); rt2x00_desc_write(txd, 1, word); - rt2x00_desc_read(txd, 2, &word); + word = rt2x00_desc_read(txd, 2); rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal); rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service); rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, @@ -1901,7 +1904,7 @@ static void rt61pci_write_tx_desc(struct queue_entry *entry, _rt2x00_desc_write(txd, 4, skbdesc->iv[1]); } - rt2x00_desc_read(txd, 5, &word); + word = rt2x00_desc_read(txd, 5); rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid); rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx); rt2x00_set_field32(&word, TXD_W5_TX_POWER, @@ -1910,12 +1913,12 @@ static void rt61pci_write_tx_desc(struct queue_entry *entry, rt2x00_desc_write(txd, 5, word); if (entry->queue->qid != QID_BEACON) { - rt2x00_desc_read(txd, 6, &word); + word = rt2x00_desc_read(txd, 6); rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS, skbdesc->skb_dma); rt2x00_desc_write(txd, 6, word); - rt2x00_desc_read(txd, 11, &word); + word = rt2x00_desc_read(txd, 11); rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, txdesc->length); rt2x00_desc_write(txd, 11, word); @@ -1926,7 +1929,7 @@ static void rt61pci_write_tx_desc(struct queue_entry *entry, * the device, whereby the device may take hold of the TXD before we * finished updating it. */ - rt2x00_desc_read(txd, 0, &word); + word = rt2x00_desc_read(txd, 0); rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); rt2x00_set_field32(&word, TXD_W0_VALID, 1); rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, @@ -1975,7 +1978,7 @@ static void rt61pci_write_beacon(struct queue_entry *entry, * Disable beaconing while we are reloading the beacon data, * otherwise we might be sending out invalid data. */ - rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); orig_reg = reg; rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); @@ -2036,7 +2039,7 @@ static void rt61pci_clear_beacon(struct queue_entry *entry) * Disable beaconing while we are reloading the beacon data, * otherwise we might be sending out invalid data. */ - rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &orig_reg); + orig_reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); reg = orig_reg; rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); @@ -2092,8 +2095,8 @@ static void rt61pci_fill_rxdone(struct queue_entry *entry, u32 word0; u32 word1; - rt2x00_desc_read(entry_priv->desc, 0, &word0); - rt2x00_desc_read(entry_priv->desc, 1, &word1); + word0 = rt2x00_desc_read(entry_priv->desc, 0); + word1 = rt2x00_desc_read(entry_priv->desc, 1); if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; @@ -2102,11 +2105,11 @@ static void rt61pci_fill_rxdone(struct queue_entry *entry, rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR); if (rxdesc->cipher != CIPHER_NONE) { - _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]); - _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]); + rxdesc->iv[0] = _rt2x00_desc_read(entry_priv->desc, 2); + rxdesc->iv[1] = _rt2x00_desc_read(entry_priv->desc, 3); rxdesc->dev_flags |= RXDONE_CRYPTO_IV; - _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv); + rxdesc->icv = _rt2x00_desc_read(entry_priv->desc, 4); rxdesc->dev_flags |= RXDONE_CRYPTO_ICV; /* @@ -2172,7 +2175,7 @@ static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev) * tx ring size for now. */ for (i = 0; i < rt2x00dev->tx->limit; i++) { - rt2x00mmio_register_read(rt2x00dev, STA_CSR4, ®); + reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR4); if (!rt2x00_get_field32(reg, STA_CSR4_VALID)) break; @@ -2195,7 +2198,7 @@ static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev) entry = &queue->entries[index]; entry_priv = entry->priv_data; - rt2x00_desc_read(entry_priv->desc, 0, &word); + word = rt2x00_desc_read(entry_priv->desc, 0); if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || !rt2x00_get_field32(word, TXD_W0_VALID)) @@ -2258,7 +2261,7 @@ static inline void rt61pci_enable_interrupt(struct rt2x00_dev *rt2x00dev, */ spin_lock_irq(&rt2x00dev->irqmask_lock); - rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); rt2x00_set_field32(®, irq_field, 0); rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); @@ -2276,7 +2279,7 @@ static void rt61pci_enable_mcu_interrupt(struct rt2x00_dev *rt2x00dev, */ spin_lock_irq(&rt2x00dev->irqmask_lock); - rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR); rt2x00_set_field32(®, irq_field, 0); rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); @@ -2328,10 +2331,10 @@ static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance) * Get the interrupt sources & saved to local variable. * Write register value back to clear pending interrupts. */ - rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®_mcu); + reg_mcu = rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR); rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu); - rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR); rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); if (!reg && !reg_mcu) @@ -2369,11 +2372,11 @@ static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance) */ spin_lock(&rt2x00dev->irqmask_lock); - rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); reg |= mask; rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); - rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR); reg |= mask_mcu; rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); @@ -2393,7 +2396,7 @@ static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) u8 *mac; s8 value; - rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR); eeprom.data = rt2x00dev; eeprom.register_read = rt61pci_eepromregister_read; @@ -2414,7 +2417,7 @@ static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); rt2x00lib_set_mac_address(rt2x00dev, mac); - rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); + word = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA); if (word == 0xffff) { rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2); rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, @@ -2429,7 +2432,7 @@ static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word); } - rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word); + word = rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC); if (word == 0xffff) { rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0); rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0); @@ -2442,7 +2445,7 @@ static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); } - rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word); + word = rt2x00_eeprom_read(rt2x00dev, EEPROM_LED); if (word == 0xffff) { rt2x00_set_field16(&word, EEPROM_LED_LED_MODE, LED_MODE_DEFAULT); @@ -2450,7 +2453,7 @@ static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) rt2x00_eeprom_dbg(rt2x00dev, "Led: 0x%04x\n", word); } - rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word); + word = rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ); if (word == 0xffff) { rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0); @@ -2458,7 +2461,7 @@ static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word); } - rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word); + word = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG); if (word == 0xffff) { rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0); rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0); @@ -2474,7 +2477,7 @@ static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); } - rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word); + word = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A); if (word == 0xffff) { rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0); rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0); @@ -2502,13 +2505,13 @@ static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev) /* * Read EEPROM word for configuration. */ - rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); + eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA); /* * Identify RF chipset. */ value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); - rt2x00mmio_register_read(rt2x00dev, MAC_CSR0, ®); + reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR0); rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), value, rt2x00_get_field32(reg, MAC_CSR0_REVISION)); @@ -2549,7 +2552,7 @@ static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev) /* * Read frequency offset and RF programming sequence. */ - rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); + eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ); if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ)) __set_bit(CAPABILITY_RF_SEQUENCE, &rt2x00dev->cap_flags); @@ -2558,7 +2561,7 @@ static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev) /* * Read external LNA informations. */ - rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); + eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC); if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A)) __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); @@ -2589,7 +2592,7 @@ static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev) * switch to default led mode. */ #ifdef CONFIG_RT2X00_LIB_LEDS - rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom); + eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_LED); value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE); rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); @@ -2850,7 +2853,7 @@ static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev) * Enable rfkill polling by setting GPIO direction of the * rfkill switch GPIO pin correctly. */ - rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, ®); + reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR13); rt2x00_set_field32(®, MAC_CSR13_DIR5, 1); rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg); @@ -2922,7 +2925,7 @@ static int rt61pci_conf_tx(struct ieee80211_hw *hw, field.bit_offset = (queue_idx & 1) * 16; field.bit_mask = 0xffff << field.bit_offset; - rt2x00mmio_register_read(rt2x00dev, offset, ®); + reg = rt2x00mmio_register_read(rt2x00dev, offset); rt2x00_set_field32(®, field, queue->txop); rt2x00mmio_register_write(rt2x00dev, offset, reg); @@ -2930,15 +2933,15 @@ static int rt61pci_conf_tx(struct ieee80211_hw *hw, field.bit_offset = queue_idx * 4; field.bit_mask = 0xf << field.bit_offset; - rt2x00mmio_register_read(rt2x00dev, AIFSN_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, AIFSN_CSR); rt2x00_set_field32(®, field, queue->aifs); rt2x00mmio_register_write(rt2x00dev, AIFSN_CSR, reg); - rt2x00mmio_register_read(rt2x00dev, CWMIN_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, CWMIN_CSR); rt2x00_set_field32(®, field, queue->cw_min); rt2x00mmio_register_write(rt2x00dev, CWMIN_CSR, reg); - rt2x00mmio_register_read(rt2x00dev, CWMAX_CSR, ®); + reg = rt2x00mmio_register_read(rt2x00dev, CWMAX_CSR); rt2x00_set_field32(®, field, queue->cw_max); rt2x00mmio_register_write(rt2x00dev, CWMAX_CSR, reg); @@ -2951,9 +2954,9 @@ static u64 rt61pci_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) u64 tsf; u32 reg; - rt2x00mmio_register_read(rt2x00dev, TXRX_CSR13, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR13); tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32; - rt2x00mmio_register_read(rt2x00dev, TXRX_CSR12, ®); + reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR12); tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER); return tsf; |