diff options
| author | Michael Chan <mchan@broadcom.com> | 2006-09-27 16:09:25 -0700 |
|---|---|---|
| committer | David S. Miller <davem@sunset.davemloft.net> | 2006-09-28 18:01:41 -0700 |
| commit | 715116a12610b67c1d301a9b845ce95f7247dad3 (patch) | |
| tree | 1f9b680e4cfc32cc7759b82481f104eae6e22f24 /drivers/net/tg3.h | |
| parent | b5d3772ccbe0bc5ac8ffbb5356b74ca698aee28c (diff) | |
| download | lwn-715116a12610b67c1d301a9b845ce95f7247dad3.tar.gz lwn-715116a12610b67c1d301a9b845ce95f7247dad3.zip | |
[TG3]: Add 5709 PHY support.
Add support for the 5709 10/100 PHY.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.h')
| -rw-r--r-- | drivers/net/tg3.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index 2f5e00c96016..9259d12fabd9 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h @@ -1624,6 +1624,7 @@ #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */ #define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */ +#define MII_TG3_EPHY_PTEST 0x17 /* 5906 PHY register */ #define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */ @@ -1637,6 +1638,8 @@ #define MII_TG3_AUX_STAT_100FULL 0x0500 #define MII_TG3_AUX_STAT_1000HALF 0x0600 #define MII_TG3_AUX_STAT_1000FULL 0x0700 +#define MII_TG3_AUX_STAT_100 0x0008 +#define MII_TG3_AUX_STAT_FULL 0x0001 #define MII_TG3_ISTAT 0x1a /* IRQ status register */ #define MII_TG3_IMASK 0x1b /* IRQ mask register */ @@ -1647,6 +1650,9 @@ #define MII_TG3_INT_DUPLEXCHG 0x0008 #define MII_TG3_INT_ANEG_PAGE_RX 0x0400 +#define MII_TG3_EPHY_TEST 0x1f /* 5906 PHY register */ +#define MII_TG3_EPHY_SHADOW_EN 0x80 + /* There are two ways to manage the TX descriptors on the tigon3. * Either the descriptors are in host DMA'able memory, or they * exist only in the cards on-chip SRAM. All 16 send bds are under |