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authorAntoine Tenart <antoine.tenart@bootlin.com>2020-01-13 23:31:48 +0100
committerDavid S. Miller <davem@davemloft.net>2020-01-14 11:31:41 -0800
commit781449a4ae3b381950ee9aec4d8a54e35f66ab9b (patch)
tree4b6237e7342ba9a11f4aa1cdd0c9f4ddccc500dc /drivers/net/phy/mscc_macsec.h
parent5c937de78b39e47ce9924fc4b863c5b727edc328 (diff)
downloadlwn-781449a4ae3b381950ee9aec4d8a54e35f66ab9b.tar.gz
lwn-781449a4ae3b381950ee9aec4d8a54e35f66ab9b.zip
net: phy: mscc: PN rollover support
This patch adds support for handling MACsec PN rollover in the mscc PHY driver. When a flow rolls over, an interrupt is fired. This patch adds the logic to check all flows and identify the one rolling over in the handle_interrupt PHY helper, then disables the flow and report the event to the MACsec core. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/phy/mscc_macsec.h')
-rw-r--r--drivers/net/phy/mscc_macsec.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/net/phy/mscc_macsec.h b/drivers/net/phy/mscc_macsec.h
index 9b5d0af91d20..d9ab6aba7482 100644
--- a/drivers/net/phy/mscc_macsec.h
+++ b/drivers/net/phy/mscc_macsec.h
@@ -83,6 +83,7 @@ enum mscc_macsec_validate_levels {
#define MSCC_MS_STATUS_CONTEXT_CTRL 0x3d02
#define MSCC_MS_INTR_CTRL_STATUS 0x3d04
#define MSCC_MS_BLOCK_CTX_UPDATE 0x3d0c
+#define MSCC_MS_AIC_CTRL 0x3e02
/* MACSEC_ENA_CFG */
#define MSCC_MS_ENA_CFG_CLK_ENA BIT(0)
@@ -260,5 +261,6 @@ enum mscc_macsec_validate_levels {
#define MSCC_MS_INTR_CTRL_STATUS_INTR_CLR_STATUS_M GENMASK(15, 0)
#define MSCC_MS_INTR_CTRL_STATUS_INTR_ENABLE(x) ((x) << 16)
#define MSCC_MS_INTR_CTRL_STATUS_INTR_ENABLE_M GENMASK(31, 16)
+#define MACSEC_INTR_CTRL_STATUS_ROLLOVER BIT(5)
#endif