diff options
| author | Guo-Fu Tseng <cooldavid@cooldavid.org> | 2011-02-13 18:27:39 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2011-02-13 20:43:22 -0800 |
| commit | 854a2e7c331a36244169626ba8e11e15d134cb5f (patch) | |
| tree | e06c5ec5967eee5d078181b0e3b8958192dfe80f /drivers/net/jme.h | |
| parent | 3903c023570446303a10f152cfc120dcbf9a4ccf (diff) | |
| download | lwn-854a2e7c331a36244169626ba8e11e15d134cb5f.tar.gz lwn-854a2e7c331a36244169626ba8e11e15d134cb5f.zip | |
jme: Safer MAC processor reset sequence
Adding control to clk_rx, and makes the control of clk_{rx|tx|tcp}
with safer sequence.
This sequence is provided by JMicron.
Signed-off-by: Guo-Fu Tseng <cooldavid@cooldavid.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/jme.h')
| -rw-r--r-- | drivers/net/jme.h | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/drivers/net/jme.h b/drivers/net/jme.h index b33bc5b0bb4e..668958c68f63 100644 --- a/drivers/net/jme.h +++ b/drivers/net/jme.h @@ -434,6 +434,7 @@ struct jme_adapter { u32 reg_rxmcs; u32 reg_ghc; u32 reg_pmcs; + u32 reg_gpreg1; u32 phylink; u32 tx_ring_size; u32 tx_ring_mask; @@ -821,6 +822,8 @@ static inline u32 smi_phy_addr(int x) */ enum jme_ghc_bit_mask { GHC_SWRST = 0x40000000, + GHC_TO_CLK_SRC = 0x00C00000, + GHC_TXMAC_CLK_SRC = 0x00300000, GHC_DPX = 0x00000040, GHC_SPEED = 0x00000030, GHC_LINK_POLL = 0x00000001, @@ -999,18 +1002,17 @@ enum jme_gpreg0_vals { /* * General Purpose REG-1 - * Note: All theses bits defined here are for - * Chip mode revision 0x11 only */ -enum jme_gpreg1_masks { +enum jme_gpreg1_bit_masks { + GPREG1_RXCLKOFF = 0x04000000, + GPREG1_PCREQN = 0x00020000, + GPREG1_HALFMODEPATCH = 0x00000040, /* For Chip revision 0x11 only */ + GPREG1_RSSPATCH = 0x00000020, /* For Chip revision 0x11 only */ GPREG1_INTRDELAYUNIT = 0x00000018, GPREG1_INTRDELAYENABLE = 0x00000007, }; enum jme_gpreg1_vals { - GPREG1_HALFMODEPATCH = 0x00000040, - GPREG1_RSSPATCH = 0x00000020, - GPREG1_INTDLYUNIT_16NS = 0x00000000, GPREG1_INTDLYUNIT_256NS = 0x00000008, GPREG1_INTDLYUNIT_1US = 0x00000010, @@ -1024,7 +1026,7 @@ enum jme_gpreg1_vals { GPREG1_INTDLYEN_6U = 0x00000006, GPREG1_INTDLYEN_7U = 0x00000007, - GPREG1_DEFAULT = 0x00000000, + GPREG1_DEFAULT = GPREG1_PCREQN, }; /* |