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| author | Ayaz Abdulla <aabdulla@nvidia.com> | 2006-07-06 16:46:25 -0400 |
|---|---|---|
| committer | Jeff Garzik <jeff@garzik.org> | 2006-07-12 17:38:20 -0400 |
| commit | 95d161cbab9d4da8b3c2d179ae11825e1294989e (patch) | |
| tree | 7d354fb522e14e6a4263fd91cf78487bed5b3798 /drivers/net/forcedeth.c | |
| parent | 9744e218aad2ef4569b0de960ff193fb50f5d6e0 (diff) | |
| download | lwn-95d161cbab9d4da8b3c2d179ae11825e1294989e.tar.gz lwn-95d161cbab9d4da8b3c2d179ae11825e1294989e.zip | |
[PATCH] forcedeth: watermark fixup
This patch defines the watermark registers and fixes up the use of this
register.
Signed-Off-By: Ayaz Abdulla <aabdulla@nvidia.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/forcedeth.c')
| -rw-r--r-- | drivers/net/forcedeth.c | 23 |
1 files changed, 19 insertions, 4 deletions
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c index 1a315d09d95e..11b8f1b43dd5 100644 --- a/drivers/net/forcedeth.c +++ b/drivers/net/forcedeth.c @@ -271,8 +271,10 @@ enum { #define NVREG_LINKSPEED_MASK (0xFFF) NvRegUnknownSetupReg5 = 0x130, #define NVREG_UNKSETUP5_BIT31 (1<<31) - NvRegUnknownSetupReg3 = 0x13c, -#define NVREG_UNKSETUP3_VAL1 0x200010 + NvRegTxWatermark = 0x13c, +#define NVREG_TX_WM_DESC1_DEFAULT 0x0200010 +#define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000 +#define NVREG_TX_WM_DESC2_3_1000 0xfe08000 NvRegTxRxControl = 0x144, #define NVREG_TXRXCTL_KICK 0x0001 #define NVREG_TXRXCTL_BIT1 0x0002 @@ -660,7 +662,7 @@ static const struct register_test nv_registers_test[] = { { NvRegMisc1, 0x03c }, { NvRegOffloadConfig, 0x03ff }, { NvRegMulticastAddrA, 0xffffffff }, - { NvRegUnknownSetupReg3, 0x0ff }, + { NvRegTxWatermark, 0x0ff }, { NvRegWakeUpFlags, 0x07777 }, { 0,0 } }; @@ -2257,6 +2259,16 @@ set_speed: } writel(txreg, base + NvRegTxDeferral); + if (np->desc_ver == DESC_VER_1) { + txreg = NVREG_TX_WM_DESC1_DEFAULT; + } else { + if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) + txreg = NVREG_TX_WM_DESC2_3_1000; + else + txreg = NVREG_TX_WM_DESC2_3_DEFAULT; + } + writel(txreg, base + NvRegTxWatermark); + writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD), base + NvRegMisc1); pci_push(base); @@ -3922,7 +3934,10 @@ static int nv_open(struct net_device *dev) /* 5) continue setup */ writel(np->linkspeed, base + NvRegLinkSpeed); - writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3); + if (np->desc_ver == DESC_VER_1) + writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark); + else + writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark); writel(np->txrxctl_bits, base + NvRegTxRxControl); writel(np->vlanctl_bits, base + NvRegVlanControl); pci_push(base); |