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| author | Hariprasad Shenai <hariprasad@chelsio.com> | 2015-02-25 16:50:04 +0530 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2015-02-27 15:53:43 -0500 |
| commit | f01aa633e040e52603b8defd2263691d15b86cb0 (patch) | |
| tree | aeeedea57fb7e650464e448463508681686f0e42 /drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | |
| parent | 2b0c2e2d2a43357fc51d3499bc405d0d05df2451 (diff) | |
| download | lwn-f01aa633e040e52603b8defd2263691d15b86cb0.tar.gz lwn-f01aa633e040e52603b8defd2263691d15b86cb0.zip | |
cxgb4: Fix PCI-E Memory window interface for big-endian systems
When doing reads and writes to adapter memory via the PCI-E Memory Window
interface, data gets swizzled on 4-byte boundaries on Big-Endian systems
because we need to account for the register read/write interface which
incorporates a swizzle onto the Little-Endian PCI-E Bus.
Based on original work by Casey Leedom <leedom@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/chelsio/cxgb4/cxgb4.h')
| -rw-r--r-- | drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h index d6cda17efe6e..97842d03675b 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h +++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h @@ -1103,7 +1103,7 @@ int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); #define T4_MEMORY_WRITE 0 #define T4_MEMORY_READ 1 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, - __be32 *buf, int dir); + void *buf, int dir); static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len, __be32 *buf) { |