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| author | Jesse Brandeburg <jesse.brandeburg@intel.com> | 2010-09-29 21:38:49 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2010-09-30 17:59:31 -0700 |
| commit | 3a3b75860527a11ba5035c6aa576079245d09e2a (patch) | |
| tree | 0dbd487fe8910a02c39ab4f84da6d16ebe6d29e3 /drivers/net/e1000e/e1000.h | |
| parent | 6af3b9ebfea38d0a057fbd7bdcecc61ac5662f02 (diff) | |
| download | lwn-3a3b75860527a11ba5035c6aa576079245d09e2a.tar.gz lwn-3a3b75860527a11ba5035c6aa576079245d09e2a.zip | |
e1000e: use hardware writeback batching
Most e1000e parts support batching writebacks. The problem with this is
that when some of the TADV or TIDV timers are not set, Tx can sit forever.
This is solved in this patch with write flushes using the Flush Partial
Descriptors (FPD) bit in TIDV and RDTR.
This improves bus utilization and removes partial writes on e1000e,
particularly from 82571 parts in S5500 chipset based machines.
Only ES2LAN and 82571/2 parts are included in this optimization, to reduce
testing load.
Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Tested-by: Emil Tantilov <emil.s.tantilov@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/e1000e/e1000.h')
| -rw-r--r-- | drivers/net/e1000e/e1000.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/drivers/net/e1000e/e1000.h b/drivers/net/e1000e/e1000.h index f9a31c82f871..5ec0af59eeab 100644 --- a/drivers/net/e1000e/e1000.h +++ b/drivers/net/e1000e/e1000.h @@ -153,6 +153,33 @@ struct e1000_info; /* Time to wait before putting the device into D3 if there's no link (in ms). */ #define LINK_TIMEOUT 100 +#define DEFAULT_RDTR 0 +#define DEFAULT_RADV 8 +#define BURST_RDTR 0x20 +#define BURST_RADV 0x20 + +/* + * in the case of WTHRESH, it appears at least the 82571/2 hardware + * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when + * WTHRESH=4, and since we want 64 bytes at a time written back, set + * it to 5 + */ +#define E1000_TXDCTL_DMA_BURST_ENABLE \ + (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \ + E1000_TXDCTL_COUNT_DESC | \ + (5 << 16) | /* wthresh must be +1 more than desired */\ + (1 << 8) | /* hthresh */ \ + 0x1f) /* pthresh */ + +#define E1000_RXDCTL_DMA_BURST_ENABLE \ + (0x01000000 | /* set descriptor granularity */ \ + (4 << 16) | /* set writeback threshold */ \ + (4 << 8) | /* set prefetch threshold */ \ + 0x20) /* set hthresh */ + +#define E1000_TIDV_FPD (1 << 31) +#define E1000_RDTR_FPD (1 << 31) + enum e1000_boards { board_82571, board_82572, @@ -425,6 +452,7 @@ struct e1000_info { #define FLAG2_DISABLE_ASPM_L1 (1 << 3) #define FLAG2_HAS_PHY_STATS (1 << 4) #define FLAG2_HAS_EEE (1 << 5) +#define FLAG2_DMA_BURST (1 << 6) #define E1000_RX_DESC_PS(R, i) \ (&(((union e1000_rx_desc_packet_split *)((R).desc))[i])) |