diff options
| author | Marc Kleine-Budde <mkl@pengutronix.de> | 2021-10-25 11:49:24 +0200 |
|---|---|---|
| committer | Marc Kleine-Budde <mkl@pengutronix.de> | 2022-03-13 09:45:36 +0100 |
| commit | aa66ae9b241eadd5d31077f869f298444c98a85f (patch) | |
| tree | e20a43155881eb0a1377d7f8e72716c10c771613 /drivers/net/can/spi | |
| parent | 656fc12ddaf8fbd126c2a56d50a9e226379cb2b0 (diff) | |
| download | lwn-aa66ae9b241eadd5d31077f869f298444c98a85f.tar.gz lwn-aa66ae9b241eadd5d31077f869f298444c98a85f.zip | |
can: mcp251xfd: ring: increase number of RX-FIFOs to 3 and increase max TX-FIFO depth to 16
This patch increases the number of RX-FIFOs to 3 and the max TX-FIFO
depth to 16. This leads to the following default ring configuration.
CAN-2.0 mode:
| FIFO setup: TEF: 0x400: 8*12 bytes = 96 bytes
| FIFO setup: RX-0: FIFO 1/0x460: 32*20 bytes = 640 bytes
| FIFO setup: RX-1: FIFO 2/0x6e0: 32*20 bytes = 640 bytes
| FIFO setup: RX-2: FIFO 3/0x960: 16*20 bytes = 320 bytes
| FIFO setup: TX: FIFO 4/0xaa0: 8*16 bytes = 128 bytes
| FIFO setup: free: 224 bytes
CAN-FD mode:
| FIFO setup: TEF: 0x400: 4*12 bytes = 48 bytes
| FIFO setup: RX-0: FIFO 1/0x430: 16*76 bytes = 1216 bytes
| FIFO setup: RX-1: FIFO 2/0x8f0: 4*76 bytes = 304 bytes
| FIFO setup: TX: FIFO 3/0xa20: 4*72 bytes = 288 bytes
| FIFO setup: free: 192 bytes
With the previously added ethtool ring configuration support the RAM
on the chip can now be runtime configured between RX and TX buffers.
Link: https://lore.kernel.org/20220313083640.501791-13-mkl@pengutronix.de
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Diffstat (limited to 'drivers/net/can/spi')
| -rw-r--r-- | drivers/net/can/spi/mcp251xfd/mcp251xfd.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd.h b/drivers/net/can/spi/mcp251xfd/mcp251xfd.h index c6cb8c3391b3..9cb6b5ad8dda 100644 --- a/drivers/net/can/spi/mcp251xfd/mcp251xfd.h +++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd.h @@ -398,7 +398,7 @@ static_assert(MCP251XFD_TIMESTAMP_WORK_DELAY_SEC < /* FIFO and Ring */ #define MCP251XFD_FIFO_TEF_NUM 1U -#define MCP251XFD_FIFO_RX_NUM 1U +#define MCP251XFD_FIFO_RX_NUM 3U #define MCP251XFD_FIFO_TX_NUM 1U #define MCP251XFD_FIFO_DEPTH 32U @@ -409,7 +409,7 @@ static_assert(MCP251XFD_TIMESTAMP_WORK_DELAY_SEC < #define MCP251XFD_RX_FIFO_DEPTH_COALESCE_MIN 8U #define MCP251XFD_TX_OBJ_NUM_MIN 2U -#define MCP251XFD_TX_OBJ_NUM_MAX 8U +#define MCP251XFD_TX_OBJ_NUM_MAX 16U #define MCP251XFD_TX_OBJ_NUM_CAN_DEFAULT 8U #define MCP251XFD_TX_OBJ_NUM_CANFD_DEFAULT 4U #define MCP251XFD_TX_FIFO_DEPTH_MIN 2U |