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author | Florian Fainelli <florian@openwrt.org> | 2010-09-08 11:11:25 +0000 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2010-09-09 21:36:36 -0700 |
commit | 3441592b34121a38047ed6680f0ed9b9017de9cf (patch) | |
tree | 62a590be79af628b4c70681585d99b36c28c6699 /drivers/net/au1000_eth.h | |
parent | b2abd4c033c3965ce670841dfb401f5f166222d5 (diff) | |
download | lwn-3441592b34121a38047ed6680f0ed9b9017de9cf.tar.gz lwn-3441592b34121a38047ed6680f0ed9b9017de9cf.zip |
au1000-eth: typedefs removal
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/au1000_eth.h')
-rw-r--r-- | drivers/net/au1000_eth.h | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/drivers/net/au1000_eth.h b/drivers/net/au1000_eth.h index d06ec008fbf1..44003e4843b8 100644 --- a/drivers/net/au1000_eth.h +++ b/drivers/net/au1000_eth.h @@ -44,34 +44,34 @@ * Data Buffer Descriptor. Data buffers must be aligned on 32 byte * boundary for both, receive and transmit. */ -typedef struct db_dest { +struct db_dest { struct db_dest *pnext; volatile u32 *vaddr; dma_addr_t dma_addr; -} db_dest_t; +}; /* * The transmit and receive descriptors are memory * mapped registers. */ -typedef struct tx_dma { +struct tx_dma { u32 status; u32 buff_stat; u32 len; u32 pad; -} tx_dma_t; +}; -typedef struct rx_dma { +struct rx_dma { u32 status; u32 buff_stat; u32 pad[2]; -} rx_dma_t; +}; /* * MAC control registers, memory mapped. */ -typedef struct mac_reg { +struct mac_reg { u32 control; u32 mac_addr_high; u32 mac_addr_low; @@ -82,16 +82,16 @@ typedef struct mac_reg { u32 flow_control; u32 vlan1_tag; u32 vlan2_tag; -} mac_reg_t; +}; struct au1000_private { - db_dest_t *pDBfree; - db_dest_t db[NUM_RX_BUFFS+NUM_TX_BUFFS]; - volatile rx_dma_t *rx_dma_ring[NUM_RX_DMA]; - volatile tx_dma_t *tx_dma_ring[NUM_TX_DMA]; - db_dest_t *rx_db_inuse[NUM_RX_DMA]; - db_dest_t *tx_db_inuse[NUM_TX_DMA]; + struct db_dest *pDBfree; + struct db_dest db[NUM_RX_BUFFS+NUM_TX_BUFFS]; + volatile struct rx_dma *rx_dma_ring[NUM_RX_DMA]; + volatile struct tx_dma *tx_dma_ring[NUM_TX_DMA]; + struct db_dest *rx_db_inuse[NUM_RX_DMA]; + struct db_dest *tx_db_inuse[NUM_TX_DMA]; u32 rx_head; u32 tx_head; u32 tx_tail; @@ -118,7 +118,7 @@ struct au1000_private { int phy_irq; /* These variables are just for quick access to certain regs addresses. */ - volatile mac_reg_t *mac; /* mac registers */ + volatile struct mac_reg *mac; /* mac registers */ volatile u32 *enable; /* address of MAC Enable Register */ u32 vaddr; /* virtual address of rx/tx buffers */ |