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author | Tal Cohen <talcohen@habana.ai> | 2022-07-07 18:42:47 +0300 |
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committer | Oded Gabbay <ogabbay@kernel.org> | 2022-09-18 13:29:51 +0300 |
commit | 194e515c79462f1ad09ebcc9e01a3acb84a98d82 (patch) | |
tree | 507354dadb1169d90633792bf2a20f10d18c206a /drivers/misc/habanalabs/include | |
parent | 07056f58e43319902cd1072c00df2846b31e14b8 (diff) | |
download | lwn-194e515c79462f1ad09ebcc9e01a3acb84a98d82.tar.gz lwn-194e515c79462f1ad09ebcc9e01a3acb84a98d82.zip |
habanalabs/gaudi2: new API to control engine cores running mode
The current flow of halting the engine cores is implemented by command
buffers built by the user space and sent towards the Driver.
This current flow is broken since the user space does not know when
the cores actually halt as sending a workload is async op.
Therefore the application can not free the memory that is mapped
to the engine cores.
This new API allows the user space to control the running mode. The
API call is sync (returns after the cores are set to the
requested mode).
Signed-off-by: Tal Cohen <talcohen@habana.ai>
Reviewed-by: Oded Gabbay <ogabbay@kernel.org>
Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
Diffstat (limited to 'drivers/misc/habanalabs/include')
-rw-r--r-- | drivers/misc/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h index d0e2c68a639f..bfda4223bdc8 100644 --- a/drivers/misc/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h @@ -239,6 +239,7 @@ #define SFT_IF_RTR_OFFSET (mmSFT0_HBW_RTR_IF1_RTR_H3_BASE - mmSFT0_HBW_RTR_IF0_RTR_H3_BASE) #define ARC_HALT_REQ_OFFSET (mmARC_FARM_ARC0_AUX_RUN_HALT_REQ - mmARC_FARM_ARC0_AUX_BASE) +#define ARC_HALT_ACK_OFFSET (mmARC_FARM_ARC0_AUX_RUN_HALT_ACK - mmARC_FARM_ARC0_AUX_BASE) #define ARC_REGION_CFG_OFFSET(region) \ (mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_0 + (region * 4) - mmARC_FARM_ARC0_AUX_BASE) |