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authorMark Brown <broonie@opensource.wolfsonmicro.com>2010-04-02 13:08:39 +0100
committerSamuel Ortiz <sameo@linux.intel.com>2010-05-13 12:58:55 +0200
commit5051d411ec87381693433d24c4488b2fa4a6306c (patch)
tree82ddb281a3bb02163af1041db8e1769274ba9814 /drivers/mfd/wm8350-core.c
parentbe835674b55324c1abe973b15343c3663910c620 (diff)
downloadlwn-5051d411ec87381693433d24c4488b2fa4a6306c.tar.gz
lwn-5051d411ec87381693433d24c4488b2fa4a6306c.zip
mfd: Clean up after WM83xx AUXADC interrupt if it arrives late
In certain circumstances, especially under heavy load, the AUXADC completion interrupt may be detected after we've timed out waiting for it. That conversion would still succeed but the next conversion will see the completion that was signalled by the interrupt for the previous conversion and therefore not wait for the AUXADC conversion to run, causing it to report failure. Provide a simple, non-invasive cleanup by using try_wait_for_completion() to ensure that the completion is not signalled before we wait. Since the AUXADC is run within a mutex we know there can only have been at most one AUXADC interrupt outstanding. A more involved change should follow for the next merge window. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat (limited to 'drivers/mfd/wm8350-core.c')
-rw-r--r--drivers/mfd/wm8350-core.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/mfd/wm8350-core.c b/drivers/mfd/wm8350-core.c
index e400a3bed063..b5807484b4c9 100644
--- a/drivers/mfd/wm8350-core.c
+++ b/drivers/mfd/wm8350-core.c
@@ -363,6 +363,10 @@ int wm8350_read_auxadc(struct wm8350 *wm8350, int channel, int scale, int vref)
reg |= 1 << channel | WM8350_AUXADC_POLL;
wm8350_reg_write(wm8350, WM8350_DIGITISER_CONTROL_1, reg);
+ /* If a late IRQ left the completion signalled then consume
+ * the completion. */
+ try_wait_for_completion(&wm8350->auxadc_done);
+
/* We ignore the result of the completion and just check for a
* conversion result, allowing us to soldier on if the IRQ
* infrastructure is not set up for the chip. */