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authorBorislav Petkov <borislav.petkov@amd.com>2009-10-16 19:55:49 +0200
committerBorislav Petkov <borislav.petkov@amd.com>2009-12-07 19:14:29 +0100
commitd16149e8c378ab7011e600980af51d2477aa5307 (patch)
treee2b28d69271d0c5afc11398ec5e97787b98ecc70 /drivers/hid
parent8566c4df1690f3862ae338a4c533f4bb5a863f9a (diff)
downloadlwn-d16149e8c378ab7011e600980af51d2477aa5307.tar.gz
lwn-d16149e8c378ab7011e600980af51d2477aa5307.zip
amd64_edac: cleanup f10_early_channel_count
Do not read DCLR[01] again since this is done in amd64_read_mc_registers() earlier. There can be more than two physical DIMMs present so clamp the channels value to max 2. Also, do not report DCT data width - it is also done earlier. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
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