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| author | Robert Beckett <robert.beckett@intel.com> | 2015-09-08 10:31:52 +0100 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-09-14 16:59:39 +0200 |
| commit | 6b6d5626750d72a22180a6e094cf95acd1d85c9b (patch) | |
| tree | 05afc0acea1e6e442bd50fbcaa1699dfa4ad9127 /drivers/gpu | |
| parent | d7884d69a524b92d9770bcdc03df3c5a6120c2d0 (diff) | |
| download | lwn-6b6d5626750d72a22180a6e094cf95acd1d85c9b.tar.gz lwn-6b6d5626750d72a22180a6e094cf95acd1d85c9b.zip | |
drm/i915/gen9: WA ST Unit Power Optimization Disable
WaDisableSTUnitPowerOptimization:skl,bxt
Signed-off-by: Robert Beckett <robert.beckett@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 495ac17b04c7..dd3d235b27ac 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6943,6 +6943,9 @@ enum skl_disp_power_wells { #define HSW_ROW_CHICKEN3 0xe49c #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) +#define HALF_SLICE_CHICKEN2 0xe180 +#define GEN8_ST_PO_DISABLE (1<<13) + #define HALF_SLICE_CHICKEN3 0xe184 #define HSW_SAMPLE_C_PERFORMANCE (1<<9) #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 684e0693dae9..16a4eada60a1 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -990,6 +990,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) GEN8_SAMPLER_POWER_BYPASS_DIS); } + /* WaDisableSTUnitPowerOptimization:skl,bxt */ + WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); + return 0; } |