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| author | Jim Bride <jim.bride@linux.intel.com> | 2015-05-27 10:21:48 -0700 |
|---|---|---|
| committer | Sasha Levin <sasha.levin@oracle.com> | 2015-07-03 12:34:43 -0400 |
| commit | 57485aa30f9ab1199b0d93cc069590864d595f3f (patch) | |
| tree | 062deb42f49e8c9cb96191fa6b151695a1c19fd3 /drivers/gpu | |
| parent | 0b89a59dd29676cac583e0e50c8dd1b269a04cd1 (diff) | |
| download | lwn-57485aa30f9ab1199b0d93cc069590864d595f3f.tar.gz lwn-57485aa30f9ab1199b0d93cc069590864d595f3f.zip | |
drm/i915/hsw: Fix workaround for server AUX channel clock divisor
[ Upstream commit e058c945e03a629c99606452a6931f632dd28903 ]
According to the HSW b-spec we need to try clock divisors of 63
and 72, each 3 or more times, when attempting DP AUX channel
communication on a server chipset. This actually wasn't happening
due to a short-circuit that only checked the DP_AUX_CH_CTL_DONE bit
in status rather than checking that the operation was done and
that DP_AUX_CH_CTL_TIME_OUT_ERROR was not set.
[v2] Implemented alternate solution suggested by Jani Nikula.
Cc: stable@vger.kernel.org
Signed-off-by: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Sasha Levin <sasha.levin@oracle.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index a29db0a1da42..3104d06aa20c 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -778,10 +778,8 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, DP_AUX_CH_CTL_RECEIVE_ERROR)) continue; if (status & DP_AUX_CH_CTL_DONE) - break; + goto done; } - if (status & DP_AUX_CH_CTL_DONE) - break; } if ((status & DP_AUX_CH_CTL_DONE) == 0) { @@ -790,6 +788,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, goto out; } +done: /* Check for timeout or receive error. * Timeouts occur when the sink is not connected */ |