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authorAlex Deucher <alexander.deucher@amd.com>2014-09-23 10:20:13 -0400
committerJiri Slaby <jslaby@suse.cz>2014-10-13 15:40:50 +0200
commit6d4933b6d7a84642bd4fe913be7182032e396e38 (patch)
treed64983b2be52d011cc18146d78815b52e5db6cda /drivers/gpu
parent07e6a67ac1cc5aa5a7cc00625170ba1ee566e5de (diff)
downloadlwn-6d4933b6d7a84642bd4fe913be7182032e396e38.tar.gz
lwn-6d4933b6d7a84642bd4fe913be7182032e396e38.zip
drm/radeon/cik: use a separate counter for CP init timeout
commit 370ce45b5986118fa496dddbcd7039e1aa1a418f upstream. Otherwise we may fail to init the second compute ring. Noticed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jiri Slaby <jslaby@suse.cz>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/radeon/cik.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 9d9770d201ae..ceba819891f4 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -3764,7 +3764,7 @@ struct bonaire_mqd
*/
static int cik_cp_compute_resume(struct radeon_device *rdev)
{
- int r, i, idx;
+ int r, i, j, idx;
u32 tmp;
bool use_doorbell = true;
u64 hqd_gpu_addr;
@@ -3887,7 +3887,7 @@ static int cik_cp_compute_resume(struct radeon_device *rdev)
mqd->queue_state.cp_hqd_pq_wptr= 0;
if (RREG32(CP_HQD_ACTIVE) & 1) {
WREG32(CP_HQD_DEQUEUE_REQUEST, 1);
- for (i = 0; i < rdev->usec_timeout; i++) {
+ for (j = 0; j < rdev->usec_timeout; j++) {
if (!(RREG32(CP_HQD_ACTIVE) & 1))
break;
udelay(1);