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| author | Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> | 2026-03-19 14:39:14 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-04-17 15:21:23 -0400 |
| commit | a0ce0de0ce9c7d60a6f22417c2237ad36687ef86 (patch) | |
| tree | ff3643e72b9c293a60cd5f891b66277ec1809aa0 /drivers/gpu/drm | |
| parent | 07ac59230d5fd603d56af2363dae80d3e973e4bc (diff) | |
| download | lwn-a0ce0de0ce9c7d60a6f22417c2237ad36687ef86.tar.gz lwn-a0ce0de0ce9c7d60a6f22417c2237ad36687ef86.zip | |
drm/amd/display: Fix DCN42 gpuvm_min_page_size_kbytes in SOC BB
[Why & How]
To match the HW specification this should be 4, not 256.
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42_soc_bb.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42_soc_bb.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42_soc_bb.h index ccdd9fd1e1bd..9ee092556233 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42_soc_bb.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42_soc_bb.h @@ -208,7 +208,7 @@ static const struct dml2_soc_bb dml2_socbb_dcn42 = { .fabric_datapath_to_dcn_data_return_bytes = 32, .return_bus_width_bytes = 64, .hostvm_min_page_size_kbytes = 4, - .gpuvm_min_page_size_kbytes = 256, + .gpuvm_min_page_size_kbytes = 4, .gpuvm_max_page_table_levels = 1, .hostvm_max_non_cached_page_table_levels = 2, .phy_downspread_percent = 0.38, |