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author | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-11-17 09:40:49 -0800 |
---|---|---|
committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 11:44:39 -0500 |
commit | 0bc519d20ffa7a450bfa21c644c2de95ae8027dc (patch) | |
tree | b56dfff2a4620146721a41a14d249bf0022ad050 /drivers/gpu/drm/xe/xe_mmio.c | |
parent | 4399e95102edfceb7a7dd7eb72cd27b776e7d38b (diff) | |
download | lwn-0bc519d20ffa7a450bfa21c644c2de95ae8027dc.tar.gz lwn-0bc519d20ffa7a450bfa21c644c2de95ae8027dc.zip |
drm/xe: Remove GEN[0-9]*_ prefixes
After noticing in logs there were still mentions to GEN6 registers, it
was clear commit d9b79ad275e7 ("drm/xe: Drop gen afixes from registers")
didn't take care of all the afixes. Some were added later, but there are
also constants and strings still using that. Continue the cleanup
removing the remaining ones.
To keep it consistent with code nearby, a few other changes are made:
- Remove prefix in INTEL_LEGACY_64B_CONTEXT
- Remove GEN8_CTX_L3LLC_COHERENT since it's unused
- Rename GEN9_FREQ_SCALER to GT_FREQUENCY_SCALER
v2: Use XELP_ as prefix for NUM_MOCS_ENTRIES and remove changes to
MOCS_ENTRIES as this is now done as part of a previous commit
(Matt Roper)
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231117174049.527192-3-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_mmio.c')
-rw-r--r-- | drivers/gpu/drm/xe/xe_mmio.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c index 0baaef53f3a7..5b24c592dde5 100644 --- a/drivers/gpu/drm/xe/xe_mmio.c +++ b/drivers/gpu/drm/xe/xe_mmio.c @@ -84,8 +84,8 @@ static void xe_resize_vram_bar(struct xe_device *xe) int i; /* gather some relevant info */ - current_size = pci_resource_len(pdev, GEN12_LMEM_BAR); - bar_size_mask = pci_rebar_get_possible_sizes(pdev, GEN12_LMEM_BAR); + current_size = pci_resource_len(pdev, LMEM_BAR); + bar_size_mask = pci_rebar_get_possible_sizes(pdev, LMEM_BAR); if (!bar_size_mask) return; @@ -137,7 +137,7 @@ static void xe_resize_vram_bar(struct xe_device *xe) pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd); pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd & ~PCI_COMMAND_MEMORY); - _resize_bar(xe, GEN12_LMEM_BAR, rebar_size); + _resize_bar(xe, LMEM_BAR, rebar_size); pci_assign_unassigned_bus_resources(pdev->bus); pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd); @@ -161,15 +161,15 @@ static int xe_determine_lmem_bar_size(struct xe_device *xe) { struct pci_dev *pdev = to_pci_dev(xe->drm.dev); - if (!xe_pci_resource_valid(pdev, GEN12_LMEM_BAR)) { + if (!xe_pci_resource_valid(pdev, LMEM_BAR)) { drm_err(&xe->drm, "pci resource is not valid\n"); return -ENXIO; } xe_resize_vram_bar(xe); - xe->mem.vram.io_start = pci_resource_start(pdev, GEN12_LMEM_BAR); - xe->mem.vram.io_size = pci_resource_len(pdev, GEN12_LMEM_BAR); + xe->mem.vram.io_start = pci_resource_start(pdev, LMEM_BAR); + xe->mem.vram.io_size = pci_resource_len(pdev, LMEM_BAR); if (!xe->mem.vram.io_size) return -EIO; @@ -216,7 +216,7 @@ static int xe_mmio_tile_vram_size(struct xe_tile *tile, u64 *vram_size, /* actual size */ if (unlikely(xe->info.platform == XE_DG1)) { - *tile_size = pci_resource_len(to_pci_dev(xe->drm.dev), GEN12_LMEM_BAR); + *tile_size = pci_resource_len(to_pci_dev(xe->drm.dev), LMEM_BAR); *tile_offset = 0; } else { reg = xe_gt_mcr_unicast_read_any(gt, XEHP_TILE_ADDR_RANGE(gt->info.id)); |