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| author | Maxime Ripard <maxime.ripard@bootlin.com> | 2019-02-11 15:41:22 +0100 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2019-02-19 11:08:17 +0100 |
| commit | 85fb352666732a9e5caf6027b9c253b3d7881d8f (patch) | |
| tree | 7062a7c5d62700de48af9833abc5c298fb0c9730 /drivers/gpu/drm/sun4i/sun4i_tcon.c | |
| parent | fd347df16d4ed2eef565344b8f16a1134bddf185 (diff) | |
| download | lwn-85fb352666732a9e5caf6027b9c253b3d7881d8f.tar.gz lwn-85fb352666732a9e5caf6027b9c253b3d7881d8f.zip | |
drm/sun4i: dsi: Restrict DSI tcon clock divider
The current code allows the TCON clock divider to have a range between 4
and 127 when feeding the DSI controller.
The only display supported so far had a display clock rate that ended up
using a divider of 4, but testing with other displays show that only 4
seems to be functional.
This also aligns with what Allwinner is doing in their BSP, so let's just
hardcode that we want a divider of 4 when using the DSI output.
Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/074e88ae472f5e0492e26939c74b44fb4125ffbd.1549896081.git-series.maxime.ripard@bootlin.com
Diffstat (limited to 'drivers/gpu/drm/sun4i/sun4i_tcon.c')
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun4i_tcon.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index 2bd2eda6480a..26f479fa6fce 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -341,8 +341,8 @@ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon, u32 block_space, start_delay; u32 tcon_div; - tcon->dclk_min_div = 4; - tcon->dclk_max_div = 127; + tcon->dclk_min_div = SUN6I_DSI_TCON_DIV; + tcon->dclk_max_div = SUN6I_DSI_TCON_DIV; sun4i_tcon0_mode_set_common(tcon, mode); |