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| author | Alex Deucher <alexdeucher@gmail.com> | 2009-07-13 11:08:18 -0400 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2009-07-15 17:13:22 +1000 |
| commit | d0e275a90a81b37409a0cfbca77581e3d235f5cf (patch) | |
| tree | 79a93ce519e39d1326bb23f38fa4549fc0950834 /drivers/gpu/drm/radeon/radeon_mode.h | |
| parent | b995e4330de0d8b1b8b9e49ce10cc6dc78e2cbba (diff) | |
| download | lwn-d0e275a90a81b37409a0cfbca77581e3d235f5cf.tar.gz lwn-d0e275a90a81b37409a0cfbca77581e3d235f5cf.zip | |
drm/radeon/kms: add PLL flag to prefer frequencies <= the target freq
This is needed when using fractional feedback dividers on some IGP
chips.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_mode.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_mode.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index 86f766e868e7..38c1dd082441 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h @@ -124,6 +124,7 @@ struct radeon_tmds_pll { #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) +#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) struct radeon_pll { uint16_t reference_freq; |