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authorJerome Glisse <jglisse@redhat.com>2013-04-09 11:17:08 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-04-11 09:22:06 -0400
commit64d7b8bed851f55a17d15ec6cc60233c85f84357 (patch)
tree82cd8c562091e6fda2419fc49002398a0d094b1c /drivers/gpu/drm/radeon/radeon.h
parent902aaef6c698ce0f04a6acab2d5396519d5de330 (diff)
downloadlwn-64d7b8bed851f55a17d15ec6cc60233c85f84357.tar.gz
lwn-64d7b8bed851f55a17d15ec6cc60233c85f84357.zip
drm/radeon: add si tile mode array query v3
Allow userspace to query for the tile mode array so userspace can properly compute surface pitch and alignment requirement depending on tiling. v2: Make strict aliasing safer by casting to char when copying v3: merge fix from Christian Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 394b20fa27dc..18904fb83d3a 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1483,6 +1483,7 @@ struct si_asic {
unsigned multi_gpu_tile_size;
unsigned tile_config;
+ uint32_t tile_mode_array[32];
};
union radeon_asic_config {