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authorAlex Deucher <alexander.deucher@amd.com>2013-06-25 17:56:16 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-06-27 19:40:05 -0400
commita9e61410921bcc1aa8f594ffa6301d5baba90f3b (patch)
tree82c267bd9854a8d0cb7b3a8ccc8693194ecfd236 /drivers/gpu/drm/radeon/r600_dpm.c
parenta0ceada6b4da18e8539bc3229adae3dc9b05d9a2 (diff)
downloadlwn-a9e61410921bcc1aa8f594ffa6301d5baba90f3b.tar.gz
lwn-a9e61410921bcc1aa8f594ffa6301d5baba90f3b.zip
drm/radeon/kms: add dpm support for SI (v7)
This adds dpm support for SI asics. This includes: - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2/gen3 switching - power containment - shader power scaling Set radeon.dpm=1 to enable. v2: enable hainan support, rebase v3: guard acpi stuff v4: fix 64 bit math v5: fix 64 bit div harder v6: fix thermal interrupt check noticed by Jerome v7: attempt fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r600_dpm.c')
-rw-r--r--drivers/gpu/drm/radeon/r600_dpm.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r600_dpm.c b/drivers/gpu/drm/radeon/r600_dpm.c
index e7684c6d07e3..76368c04f809 100644
--- a/drivers/gpu/drm/radeon/r600_dpm.c
+++ b/drivers/gpu/drm/radeon/r600_dpm.c
@@ -906,6 +906,7 @@ int r600_parse_extended_power_table(struct radeon_device *rdev)
sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE5)) {
rdev->pm.dpm.tdp_limit = le32_to_cpu(power_info->pplib5.ulTDPLimit);
rdev->pm.dpm.near_tdp_limit = le32_to_cpu(power_info->pplib5.ulNearTDPLimit);
+ rdev->pm.dpm.near_tdp_limit_adjusted = rdev->pm.dpm.near_tdp_limit;
rdev->pm.dpm.tdp_od_limit = le16_to_cpu(power_info->pplib5.usTDPODLimit);
if (rdev->pm.dpm.tdp_od_limit)
rdev->pm.dpm.power_control = true;