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author | Michel Dänzer <michel.daenzer@amd.com> | 2013-11-18 18:26:00 +0900 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2013-11-18 09:19:36 -0500 |
commit | 32f79a8a82b2ff6f1828b258da214869adc2a28c (patch) | |
tree | 660ce0abbf61ca8d13a8d8d5c7c2d98199d856f3 /drivers/gpu/drm/radeon/cik.c | |
parent | 1ddce27d8f0ae3f911850e06a4937de89645dfa7 (diff) | |
download | lwn-32f79a8a82b2ff6f1828b258da214869adc2a28c.tar.gz lwn-32f79a8a82b2ff6f1828b258da214869adc2a28c.zip |
drm/radeon/cik: Add macrotile mode array query
This is required to properly calculate the tiling parameters
in userspace.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/cik.c')
-rw-r--r-- | drivers/gpu/drm/radeon/cik.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 08aa58ef8d0a..b43a3a3c9067 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -2427,6 +2427,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) gb_tile_moden = 0; break; } + rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden; WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); } } else if (num_pipe_configs == 4) { @@ -2773,6 +2774,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) gb_tile_moden = 0; break; } + rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden; WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); } } else if (num_pipe_configs == 2) { @@ -2990,6 +2992,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) gb_tile_moden = 0; break; } + rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden; WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); } } else |