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authorAkhil P Oommen <akhilpo@oss.qualcomm.com>2025-09-08 13:57:06 +0530
committerRob Clark <robin.clark@oss.qualcomm.com>2025-09-08 07:25:00 -0700
commit62cd0fa6990b03d6618e9031d926a2f672a3d801 (patch)
tree1cc249553e6eb67d7b8b413b5878d37aa4b69bbd /drivers/gpu/drm/msm/msm_submitqueue.c
parenta242ef4a7577bfd3dbf0b4fb7bf92adca145b0c1 (diff)
downloadlwn-62cd0fa6990b03d6618e9031d926a2f672a3d801.tar.gz
lwn-62cd0fa6990b03d6618e9031d926a2f672a3d801.zip
drm/msm/adreno: Disable IFPC when sysprof is active
Moving to IFPC state clears the 'Perfcounter Select' register setup by the userspace. So, lets block the IFPC when sysprof is active by using the perfcounter oob signal to the GMU. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/673380/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Diffstat (limited to 'drivers/gpu/drm/msm/msm_submitqueue.c')
-rw-r--r--drivers/gpu/drm/msm/msm_submitqueue.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c b/drivers/gpu/drm/msm/msm_submitqueue.c
index 8617a82cd6b3..d53dfad16bde 100644
--- a/drivers/gpu/drm/msm/msm_submitqueue.c
+++ b/drivers/gpu/drm/msm/msm_submitqueue.c
@@ -40,6 +40,10 @@ int msm_context_set_sysprof(struct msm_context *ctx, struct msm_gpu *gpu, int sy
break;
}
+ /* Some gpu families require additional setup for sysprof */
+ if (gpu->funcs->sysprof_setup)
+ gpu->funcs->sysprof_setup(gpu);
+
ctx->sysprof = sysprof;
return 0;