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| author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2011-09-02 12:54:37 -0700 |
|---|---|---|
| committer | Keith Packard <keithp@keithp.com> | 2011-10-20 15:26:42 -0700 |
| commit | 27f8227b1e2b326a9a0995dd9c1f14893c61ee01 (patch) | |
| tree | 2158d909c7e960fc84c97b79a5c1069b828e3512 /drivers/gpu/drm/i915/intel_sdvo.c | |
| parent | 4c609cb890b13ef58e0c0cdd238993484e1b9b83 (diff) | |
| download | lwn-27f8227b1e2b326a9a0995dd9c1f14893c61ee01.tar.gz lwn-27f8227b1e2b326a9a0995dd9c1f14893c61ee01.zip | |
drm/i915: support 3 pipes on IVB+
Well almost anyway. IVB has 3 planes, pipes, transcoders, and FDI
interfaces, but only 2 pipe PLLs. So two of the pipes must use the same
pipe timings (e.g. 2 DP plus one other, or two HDMI with the same mode
and one other, etc.).
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-By: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-By: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_sdvo.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_sdvo.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 1b97d1f48fb0..6db3b1ccb6eb 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -2203,7 +2203,7 @@ intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) bytes[0], bytes[1]); return false; } - intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1); + intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); return true; } |