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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2013-11-28 17:29:58 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-12-04 12:09:35 +0100 |
| commit | c5a44aa012ee86b3dfd0c6050ba34cd6eb412875 (patch) | |
| tree | 809dcb1a8fca2047127591179d912abdc1e1de7e /drivers/gpu/drm/i915/intel_pm.c | |
| parent | 82f344967cca4d4d0bd3cbcdeddfc6bf00a46fd8 (diff) | |
| download | lwn-c5a44aa012ee86b3dfd0c6050ba34cd6eb412875.tar.gz lwn-c5a44aa012ee86b3dfd0c6050ba34cd6eb412875.zip | |
drm/i915: Fix FBC1 plane checks for gen2
On gen2 and gen3 chipsets FBC is supported only on plane A. Fix (and
simplify) the plane checks in intel_update_fbc() accordingly.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ff47520f8d40..d389078f0fe1 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -537,10 +537,10 @@ void intel_update_fbc(struct drm_device *dev) DRM_DEBUG_KMS("mode too large for compression, disabling\n"); goto out_disable; } - if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) && - intel_crtc->plane != 0) { + if ((INTEL_INFO(dev)->gen < 4 || IS_HASWELL(dev)) && + intel_crtc->plane != PLANE_A) { if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE)) - DRM_DEBUG_KMS("plane not 0, disabling compression\n"); + DRM_DEBUG_KMS("plane not A, disabling compression\n"); goto out_disable; } |