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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2014-02-04 21:59:19 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-03-04 15:39:05 +0100 |
| commit | a607c1a41d7dae073d6b79460b26e818c772984e (patch) | |
| tree | 817bb60d977096ebb5e216b77e87442819bd6a9c /drivers/gpu/drm/i915/intel_pm.c | |
| parent | 743b57d830b8834026508050bd138c1247fccd4a (diff) | |
| download | lwn-a607c1a41d7dae073d6b79460b26e818c772984e.tar.gz lwn-a607c1a41d7dae073d6b79460b26e818c772984e.zip | |
drm/i915: Change IVB WIZ hashing mode to 16x4
BSpec recommends using 8x4 hashing mode when MSAA is used. But in
practice 16x4 seems to have a slight edge in performance (on IVB and
HSW at least). So just use 16x4.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 08c1a756cdad..57101f2321fd 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4954,6 +4954,13 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) I915_WRITE(CACHE_MODE_1, _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); + /* + * BSpec recommends 8x4 when MSAA is used, + * however in practice 16x4 seems fastest. + */ + I915_WRITE(GEN7_GT_MODE, + GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); + snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); snpcr &= ~GEN6_MBC_SNPCR_MASK; snpcr |= GEN6_MBC_SNPCR_MED; |